URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] [scr1_timer.sv] - Diff between revs 11 and 21

Rev 11	Rev 21
Line 12...	Line 12...
`input logic clk,`	`input logic clk,`
`input logic rtc_clk,`	`input logic rtc_clk,`

`// Memory interface`	`// Memory interface`
`input logic dmem_req,`	`input logic dmem_req,`
`input type_scr1_mem_cmd_e dmem_cmd,`	`input logic dmem_cmd,`
`input type_scr1_mem_width_e dmem_width,`	`input logic [1:0] dmem_width,`
input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,	input logic [`SCR1_DMEM_AWIDTH-1:0] dmem_addr,
input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,	input logic [`SCR1_DMEM_DWIDTH-1:0] dmem_wdata,
`output logic dmem_req_ack,`	`output logic dmem_req_ack,`
output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,	output logic [`SCR1_DMEM_DWIDTH-1:0] dmem_rdata,
`output type_scr1_mem_resp_e dmem_resp,`	`output logic [1:0] dmem_resp,`

`// Timer interface`	`// Timer interface`
`output logic [63:0] timer_val,`	`output logic [63:0] timer_val,`
`output logic timer_irq`	`output logic timer_irq`
`);`	`);`