Line 166... |
Line 166... |
`endif // SCR1_DBG_EN
|
`endif // SCR1_DBG_EN
|
|
|
// Instruction memory interface from core to router
|
// Instruction memory interface from core to router
|
logic core_imem_req_ack;
|
logic core_imem_req_ack;
|
logic core_imem_req;
|
logic core_imem_req;
|
type_scr1_mem_cmd_e core_imem_cmd;
|
logic core_imem_cmd;
|
logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
|
logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
|
logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
|
logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
|
type_scr1_mem_resp_e core_imem_resp;
|
logic [1:0] core_imem_resp;
|
|
|
// Data memory interface from core to router
|
// Data memory interface from core to router
|
logic core_dmem_req_ack;
|
logic core_dmem_req_ack;
|
logic core_dmem_req;
|
logic core_dmem_req;
|
type_scr1_mem_cmd_e core_dmem_cmd;
|
logic core_dmem_cmd;
|
type_scr1_mem_width_e core_dmem_width;
|
logic [1:0] core_dmem_width;
|
logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
|
logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
|
logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
|
type_scr1_mem_resp_e core_dmem_resp;
|
logic [1:0] core_dmem_resp;
|
|
|
// Instruction memory interface from router to AXI bridge
|
// Instruction memory interface from router to AXI bridge
|
logic axi_imem_req_ack;
|
logic axi_imem_req_ack;
|
logic axi_imem_req;
|
logic axi_imem_req;
|
type_scr1_mem_cmd_e axi_imem_cmd;
|
logic axi_imem_cmd;
|
logic [`SCR1_IMEM_AWIDTH-1:0] axi_imem_addr;
|
logic [`SCR1_IMEM_AWIDTH-1:0] axi_imem_addr;
|
logic [`SCR1_IMEM_DWIDTH-1:0] axi_imem_rdata;
|
logic [`SCR1_IMEM_DWIDTH-1:0] axi_imem_rdata;
|
type_scr1_mem_resp_e axi_imem_resp;
|
logic [1:0] axi_imem_resp;
|
|
|
// Data memory interface from router to AXI bridge
|
// Data memory interface from router to AXI bridge
|
logic axi_dmem_req_ack;
|
logic axi_dmem_req_ack;
|
logic axi_dmem_req;
|
logic axi_dmem_req;
|
type_scr1_mem_cmd_e axi_dmem_cmd;
|
logic axi_dmem_cmd;
|
type_scr1_mem_width_e axi_dmem_width;
|
logic [1:0] axi_dmem_width;
|
logic [`SCR1_DMEM_AWIDTH-1:0] axi_dmem_addr;
|
logic [`SCR1_DMEM_AWIDTH-1:0] axi_dmem_addr;
|
logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_wdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_wdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_rdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] axi_dmem_rdata;
|
type_scr1_mem_resp_e axi_dmem_resp;
|
logic [1:0] axi_dmem_resp;
|
|
|
`ifdef SCR1_TCM_EN
|
`ifdef SCR1_TCM_EN
|
// Instruction memory interface from router to TCM
|
// Instruction memory interface from router to TCM
|
logic tcm_imem_req_ack;
|
logic tcm_imem_req_ack;
|
logic tcm_imem_req;
|
logic tcm_imem_req;
|
type_scr1_mem_cmd_e tcm_imem_cmd;
|
logic tcm_imem_cmd;
|
logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
|
logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
|
logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
|
logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
|
type_scr1_mem_resp_e tcm_imem_resp;
|
logic [1:0] tcm_imem_resp;
|
|
|
// Data memory interface from router to TCM
|
// Data memory interface from router to TCM
|
logic tcm_dmem_req_ack;
|
logic tcm_dmem_req_ack;
|
logic tcm_dmem_req;
|
logic tcm_dmem_req;
|
type_scr1_mem_cmd_e tcm_dmem_cmd;
|
logic tcm_dmem_cmd;
|
type_scr1_mem_width_e tcm_dmem_width;
|
logic [1:0] tcm_dmem_width;
|
logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
|
logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
|
logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
|
type_scr1_mem_resp_e tcm_dmem_resp;
|
logic [1:0] tcm_dmem_resp;
|
`endif // SCR1_TCM_EN
|
`endif // SCR1_TCM_EN
|
|
|
// Data memory interface from router to memory-mapped timer
|
// Data memory interface from router to memory-mapped timer
|
logic timer_dmem_req_ack;
|
logic timer_dmem_req_ack;
|
logic timer_dmem_req;
|
logic timer_dmem_req;
|
type_scr1_mem_cmd_e timer_dmem_cmd;
|
logic timer_dmem_cmd;
|
type_scr1_mem_width_e timer_dmem_width;
|
logic [1:0] timer_dmem_width;
|
logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
|
logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
|
logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
|
logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
|
type_scr1_mem_resp_e timer_dmem_resp;
|
logic [1:0] timer_dmem_resp;
|
|
|
// Misc
|
// Misc
|
logic timer_irq;
|
logic timer_irq;
|
logic [63:0] timer_val;
|
logic [63:0] timer_val;
|
logic axi_reinit;
|
logic axi_reinit;
|