| Line 142... |
Line 142... |
`endif // SCR1_DBG_EN
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`endif // SCR1_DBG_EN
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// Instruction memory interface from core to router
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// Instruction memory interface from core to router
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logic core_imem_req_ack;
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logic core_imem_req_ack;
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logic core_imem_req;
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logic core_imem_req;
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type_scr1_mem_cmd_e core_imem_cmd;
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logic core_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
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logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
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logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata;
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type_scr1_mem_resp_e core_imem_resp;
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logic [1:0] core_imem_resp;
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// Data memory interface from core to router
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// Data memory interface from core to router
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logic core_dmem_req_ack;
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logic core_dmem_req_ack;
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logic core_dmem_req;
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logic core_dmem_req;
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type_scr1_mem_cmd_e core_dmem_cmd;
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logic core_dmem_cmd;
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type_scr1_mem_width_e core_dmem_width;
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logic [1:0] core_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
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logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
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type_scr1_mem_resp_e core_dmem_resp;
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logic [1:0] core_dmem_resp;
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// Instruction memory interface from router to WB bridge
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// Instruction memory interface from router to WB bridge
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logic wb_imem_req_ack;
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logic wb_imem_req_ack;
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logic wb_imem_req;
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logic wb_imem_req;
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type_scr1_mem_cmd_e wb_imem_cmd;
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logic wb_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] wb_imem_addr;
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logic [`SCR1_IMEM_AWIDTH-1:0] wb_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] wb_imem_rdata;
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logic [`SCR1_IMEM_DWIDTH-1:0] wb_imem_rdata;
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type_scr1_mem_resp_e wb_imem_resp;
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logic [1:0] wb_imem_resp;
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// Data memory interface from router to WB bridge
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// Data memory interface from router to WB bridge
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logic wb_dmem_req_ack;
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logic wb_dmem_req_ack;
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logic wb_dmem_req;
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logic wb_dmem_req;
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type_scr1_mem_cmd_e wb_dmem_cmd;
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logic wb_dmem_cmd;
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type_scr1_mem_width_e wb_dmem_width;
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logic [1:0] wb_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] wb_dmem_addr;
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logic [`SCR1_DMEM_AWIDTH-1:0] wb_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_rdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_rdata;
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type_scr1_mem_resp_e wb_dmem_resp;
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logic [1:0] wb_dmem_resp;
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`ifdef SCR1_TCM_EN
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`ifdef SCR1_TCM_EN
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// Instruction memory interface from router to TCM
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// Instruction memory interface from router to TCM
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logic tcm_imem_req_ack;
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logic tcm_imem_req_ack;
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logic tcm_imem_req;
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logic tcm_imem_req;
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type_scr1_mem_cmd_e tcm_imem_cmd;
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logic tcm_imem_cmd;
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logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
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logic [`SCR1_IMEM_AWIDTH-1:0] tcm_imem_addr;
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logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
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logic [`SCR1_IMEM_DWIDTH-1:0] tcm_imem_rdata;
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type_scr1_mem_resp_e tcm_imem_resp;
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logic [1:0] tcm_imem_resp;
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// Data memory interface from router to TCM
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// Data memory interface from router to TCM
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logic tcm_dmem_req_ack;
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logic tcm_dmem_req_ack;
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logic tcm_dmem_req;
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logic tcm_dmem_req;
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type_scr1_mem_cmd_e tcm_dmem_cmd;
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logic tcm_dmem_cmd;
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type_scr1_mem_width_e tcm_dmem_width;
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logic [1:0] tcm_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
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logic [`SCR1_DMEM_AWIDTH-1:0] tcm_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] tcm_dmem_rdata;
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type_scr1_mem_resp_e tcm_dmem_resp;
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logic [1:0] tcm_dmem_resp;
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`endif // SCR1_TCM_EN
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`endif // SCR1_TCM_EN
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// Data memory interface from router to memory-mapped timer
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// Data memory interface from router to memory-mapped timer
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logic timer_dmem_req_ack;
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logic timer_dmem_req_ack;
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logic timer_dmem_req;
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logic timer_dmem_req;
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type_scr1_mem_cmd_e timer_dmem_cmd;
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logic timer_dmem_cmd;
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type_scr1_mem_width_e timer_dmem_width;
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logic [1:0] timer_dmem_width;
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logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
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logic [`SCR1_DMEM_AWIDTH-1:0] timer_dmem_addr;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_wdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
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logic [`SCR1_DMEM_DWIDTH-1:0] timer_dmem_rdata;
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type_scr1_mem_resp_e timer_dmem_resp;
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logic [1:0] timer_dmem_resp;
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logic timer_irq;
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logic timer_irq;
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logic [63:0] timer_val;
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logic [63:0] timer_val;
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| Line 472... |
Line 472... |
.port1_req ( ),
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.port1_req ( ),
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.port1_cmd ( ),
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.port1_cmd ( ),
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.port1_width ( ),
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.port1_width ( ),
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.port1_addr ( ),
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.port1_addr ( ),
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.port1_wdata ( ),
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.port1_wdata ( ),
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.port1_rdata ('0 ),
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.port1_rdata (32'h0 ),
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.port1_resp (SCR1_MEM_RESP_RDY_ER),
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.port1_resp (SCR1_MEM_RESP_RDY_ER),
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`endif // SCR1_TCM_EN
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`endif // SCR1_TCM_EN
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// Interface to memory-mapped timer
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// Interface to memory-mapped timer
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.port2_req_ack (timer_dmem_req_ack ),
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.port2_req_ack (timer_dmem_req_ack ),
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.port2_req (timer_dmem_req ),
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.port2_req (timer_dmem_req ),
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