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Line 22... |
`default_nettype wire
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`default_nettype wire
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`include "gl/user_project_wrapper.v"
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`include "gl/user_project_wrapper.v"
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`include "gl/user_proj_example.v"
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`include "gl/user_proj_example.v"
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`else
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`else
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`include "user_project_wrapper.v"
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`include "user_project_wrapper.v"
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`include "user_proj_example.v"
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`include "spi_master/src/spim_top.sv"
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`include "spi_master/src/spim_regs.sv"
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`include "spi_master/src/spim_clkgen.sv"
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`include "spi_master/src/spim_ctrl.sv"
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`include "spi_master/src/spim_rx.sv"
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`include "spi_master/src/spim_tx.sv"
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`include "sdram_ctrl/src/top/sdrc_top.v"
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`include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
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`include "lib/async_fifo.sv"
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`include "sdram_ctrl/src/core/sdrc_core.v"
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`include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
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`include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
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`include "sdram_ctrl/src/core/sdrc_bs_convert.v"
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`include "sdram_ctrl/src/core/sdrc_req_gen.v"
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`include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
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`include "lib/registers.v"
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`include "lib/clk_ctl.v"
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`include "digital_core/src/glbl_cfg.sv"
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`include "digital_core/src/digital_core.sv"
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`include "wb_interconnect/src/wb_arb.sv"
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`include "wb_interconnect/src/wb_interconnect.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
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`include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
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`include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
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`include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
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`include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
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`include "syntacore/scr1/src/core/scr1_tapc.sv"
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`include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
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`include "syntacore/scr1/src/core/scr1_core_top.sv"
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`include "syntacore/scr1/src/core/scr1_dm.sv"
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`include "syntacore/scr1/src/core/scr1_dmi.sv"
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`include "syntacore/scr1/src/core/scr1_scu.sv"
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`include "syntacore/scr1/src/top/scr1_dmem_router.sv"
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`include "syntacore/scr1/src/top/scr1_dp_memory.sv"
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`include "syntacore/scr1/src/top/scr1_tcm.sv"
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`include "syntacore/scr1/src/top/scr1_timer.sv"
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`include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
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`include "syntacore/scr1/src/top/scr1_imem_wb.sv"
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`include "syntacore/scr1/src/top/scr1_top_wb.sv"
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`include "lib/sync_fifo.sv"
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`endif
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`endif
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