| Line 26... |
Line 26... |
* example should be removed and replaced with the actual
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* example should be removed and replaced with the actual
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* user project.
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* user project.
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*
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*
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*-------------------------------------------------------------
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*-------------------------------------------------------------
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*/
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*/
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`default_nettype wire
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module user_project_wrapper #(
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module user_project_wrapper #(
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parameter BITS = 32
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parameter BITS = 32
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) (
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) (
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`ifdef USE_POWER_PINS
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`ifdef USE_POWER_PINS
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inout vdda1, // User area 1 3.3V supply
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inout vdda1, // User area 1 3.3V supply
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| Line 76... |
Line 76... |
|
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// User maskable interrupt signals
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// User maskable interrupt signals
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output [2:0] user_irq
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output [2:0] user_irq
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);
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);
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|
|
|
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/*--------------------------------------*/
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/*--------------------------------------*/
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/* User project is instantiated here */
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/* User project is instantiated here */
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/*--------------------------------------*/
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/*--------------------------------------*/
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|
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user_proj_example mprj (
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digital_core u_core (
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`ifdef USE_POWER_PINS
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`ifdef USE_POWER_PINS
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.vdda1(vdda1), // User area 1 3.3V power
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.vdda1(vdda1), // User area 1 3.3V power
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.vdda2(vdda2), // User area 2 3.3V power
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.vdda2(vdda2), // User area 2 3.3V power
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.vssa1(vssa1), // User area 1 analog ground
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.vssa1(vssa1), // User area 1 analog ground
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.vssa2(vssa2), // User area 2 analog ground
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.vssa2(vssa2), // User area 2 analog ground
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| Line 92... |
Line 93... |
.vccd2(vccd2), // User area 2 1.8V power
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.vccd2(vccd2), // User area 2 1.8V power
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.vssd1(vssd1), // User area 1 digital ground
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.vssd1(vssd1), // User area 1 digital ground
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.vssd2(vssd2), // User area 2 digital ground
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.vssd2(vssd2), // User area 2 digital ground
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`endif
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`endif
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|
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.wb_clk_i(wb_clk_i),
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.clk(wb_clk_i),
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.wb_rst_i(wb_rst_i),
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.rst_n(!wb_rst_i),
|
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.rtc_clk(user_clock2),
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|
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// MGMT SoC Wishbone Slave
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// MGMT SoC Wishbone Slave
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|
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.wbs_cyc_i(wbs_cyc_i),
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.wbd_ext_cyc_i(wbs_cyc_i),
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.wbs_stb_i(wbs_stb_i),
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.wbd_ext_stb_i(wbs_stb_i),
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.wbs_we_i(wbs_we_i),
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.wbd_ext_we_i(wbs_we_i),
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.wbs_sel_i(wbs_sel_i),
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.wbd_ext_sel_i(wbs_sel_i),
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.wbs_adr_i(wbs_adr_i),
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.wbd_ext_adr_i(wbs_adr_i),
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.wbs_dat_i(wbs_dat_i),
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.wbd_ext_dat_i(wbs_dat_i),
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.wbs_ack_o(wbs_ack_o),
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.wbd_ext_ack_o(wbs_ack_o),
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.wbs_dat_o(wbs_dat_o),
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.wbd_ext_dat_o(wbs_dat_o),
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.wbd_ext_err_o(),
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|
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// Logic Analyzer
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// Logic Analyzer
|
|
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.la_data_in(la_data_in),
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.la_data_in(la_data_in),
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.la_data_out(la_data_out),
|
.la_data_out(la_data_out),
|
