## *ZAP* : An ARM compatible core with cache and MMU (ARMv4T ISA compatible)
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## *ZAP* : An ARM compatible core with cache and MMU (ARMv4T ISA compatible)
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#### Author : Revanth Kamaraj (revanth91kamaraj@gmail.com)
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#### Author : Revanth Kamaraj (revanth91kamaraj@gmail.com)
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#### License : GPL v2
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#### License : GPL v2
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### Description
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### Description
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ZAP is a pipelined ARM processor core that can execute the ARMv4T instruction
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ZAP is a pipelined ARM processor core that can execute the ARMv4T instruction
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set. It is equipped with ARMv4 compatible split writeback caches and memory
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set. It is equipped with ARMv4 compatible split writeback caches and memory
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management capabilities. The processor core uses a 10 stage pipeline.
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management capabilities. The processor core uses a 10 stage pipeline.
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Note that ARM GCC is included in the repository in the *sw* directory. The
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Note that ARM GCC is included in the repository in the *sw* directory. The
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makefile will extract the GCC compiler into the object folder.
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makefile will extract the GCC compiler into the object folder.
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### Current Status
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### Current Status
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Experimental.
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Experimental.
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### Bugs and Known Issues
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### Bugs and Known Issues
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- Issues with the Thumb ISA.
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- Issues with the Thumb ISA.
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- SWAP does not bypass cache.
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- SWAP does not bypass cache.
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### Bus Interface
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### Bus Interface
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Wishbone B3 compatible 32-bit bus.
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Wishbone B3 compatible 32-bit bus.
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### Documentation
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### Documentation
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Please see the PDF file at *doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf*
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Please see the PDF file at *doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf*
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### Features
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### Features
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- Fully synthesizable Verilog-2001 core.
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- Fully synthesizable Verilog-2001 core.
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- Store buffer for improved performance.
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- Store buffer for improved performance.
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- Can execute ARMv4T code. Note that compressed instruction support is EXPERIMENTAL.
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- Can execute ARMv4T code. Note that compressed instruction support is EXPERIMENTAL.
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- Wishbone B3 compatible interface. Cache unit supports burst access.
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- Wishbone B3 compatible interface. Cache unit supports burst access.
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- 10-stage pipeline design. Pipeline has bypass network to resolve dependencies.
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- 10-stage pipeline design. Pipeline has bypass network to resolve dependencies.
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- 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
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- 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
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- Branch prediction supported.
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- Branch prediction supported.
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- Split I and D writeback cache (Size can be configured using parameters).
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- Split I and D writeback cache (Size can be configured using parameters).
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- Split I and D MMUs (TLB size can be configured using parameters).
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- Split I and D MMUs (TLB size can be configured using parameters).
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- Base restored abort model to simplify data abort handling.
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- Base restored abort model to simplify data abort handling.
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### License
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(C) 2016-2018 Revanth Kamaraj.
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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