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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_cache_fsm.v] - Diff between revs 43 and 51

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Rev 43 Rev 51
Line 122... Line 122...
localparam REFRESH              = 5; /* Cache refresh parent state */
localparam REFRESH              = 5; /* Cache refresh parent state */
localparam INVALIDATE           = 6; /* Cache invalidate parent state */
localparam INVALIDATE           = 6; /* Cache invalidate parent state */
localparam CLEAN                = 7; /* Cache clean parent state */
localparam CLEAN                = 7; /* Cache clean parent state */
localparam NUMBER_OF_STATES     = 8;
localparam NUMBER_OF_STATES     = 8;
 
 
// ---------------------------------------------------------------
// ----------------------------------------------------------------------------
// Signal aliases   
// Signal aliases   
// ---------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
wire cache_cmp   = (i_cache_tag[`CACHE_TAG__TAG] == i_address[`VA__CACHE_TAG]);
wire cache_cmp   = (i_cache_tag[`CACHE_TAG__TAG] == i_address[`VA__CACHE_TAG]);
wire cache_dirty = i_cache_tag_dirty;
wire cache_dirty = i_cache_tag_dirty;
 
 
// ---------------------------------------------------------------
// ----------------------------------------------------------------------------
// Variables
// Variables
// ---------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
reg [$clog2(NUMBER_OF_STATES)-1:0]      state_ff, state_nxt;
reg [$clog2(NUMBER_OF_STATES)-1:0]      state_ff, state_nxt;
reg [31:0]                              buf_ff [3:0];
reg [31:0]                              buf_ff [3:0];
reg [31:0]                              buf_nxt[3:0];
reg [31:0]                              buf_nxt[3:0];
reg                                     cache_clean_req_nxt,
reg                                     cache_clean_req_nxt,
Line 143... Line 143...
reg                                     cache_inv_req_nxt,
reg                                     cache_inv_req_nxt,
                                        cache_inv_req_ff;
                                        cache_inv_req_ff;
reg [2:0]                               adr_ctr_ff, adr_ctr_nxt; // Needs to take on 0,1,2,3 AND 4(nxt).
reg [2:0]                               adr_ctr_ff, adr_ctr_nxt; // Needs to take on 0,1,2,3 AND 4(nxt).
reg                                     hit;                     // For debug only.
reg                                     hit;                     // For debug only.
 
 
// ----------------------------------------------------------------
// ----------------------------------------------------------------------------
// Logic
// Logic
// ----------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
/* Tie flops to the output */
/* Tie flops to the output */
always @* o_cache_clean_req = cache_clean_req_ff; // Tie req flop to output.
always @* o_cache_clean_req = cache_clean_req_ff; // Tie req flop to output.
always @* o_cache_inv_req = cache_inv_req_ff;     // Tie inv flop to output.
always @* o_cache_inv_req = cache_inv_req_ff;     // Tie inv flop to output.
 
 
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        end
        end
 
 
        endcase
        endcase
end
end
 
 
// ------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Tasks and functions.
// Tasks and functions.
// ------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
function [31:0] adapt_cache_data
function [31:0] adapt_cache_data
(input [1:0] shift, input [127:0] cd);
(input [1:0] shift, input [127:0] cd);
begin: blk1
begin: blk1
        reg [31:0] shamt;
        reg [31:0] shamt;
Line 501... Line 501...
/* Function to generate Wishbone read signals. */
/* Function to generate Wishbone read signals. */
task  wb_prpr_read;
task  wb_prpr_read;
input [31:0] i_address;
input [31:0] i_address;
input [2:0]  i_cti;
input [2:0]  i_cti;
begin
begin
        $display($time, " - %m :: Reading from address %x", i_address);
 
 
 
        o_wb_cyc_nxt = 1'd1;
        o_wb_cyc_nxt = 1'd1;
        o_wb_stb_nxt = 1'd1;
        o_wb_stb_nxt = 1'd1;
        o_wb_wen_nxt = 1'd0;
        o_wb_wen_nxt = 1'd0;
        o_wb_sel_nxt = 4'b1111;
        o_wb_sel_nxt = 4'b1111;
        o_wb_adr_nxt = i_address;
        o_wb_adr_nxt = i_address;
Line 520... Line 518...
input   [31:0]  i_data;
input   [31:0]  i_data;
input   [31:0]  i_address;
input   [31:0]  i_address;
input   [2:0]   i_cti;
input   [2:0]   i_cti;
input   [3:0]   i_ben;
input   [3:0]   i_ben;
begin
begin
        $display($time, " - %m :: Writing to address %x with ben = %x", i_address, i_ben);
 
 
 
        o_wb_cyc_nxt = 1'd1;
        o_wb_cyc_nxt = 1'd1;
        o_wb_stb_nxt = 1'd1;
        o_wb_stb_nxt = 1'd1;
        o_wb_wen_nxt = 1'd1;
        o_wb_wen_nxt = 1'd1;
        o_wb_sel_nxt = i_ben;
        o_wb_sel_nxt = i_ben;
        o_wb_adr_nxt = i_address;
        o_wb_adr_nxt = i_address;
Line 547... Line 543...
end
end
endtask
endtask
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
// synopsys translate_off
 
 
 
wire [31:0] buf0_ff, buf1_ff, buf2_ff;
wire [31:0] buf0_ff, buf1_ff, buf2_ff;
 
 
assign buf0_ff = buf_ff[0];
assign buf0_ff = buf_ff[0];
assign buf1_ff = buf_ff[1];
assign buf1_ff = buf_ff[1];
assign buf2_ff = buf_ff[2];
assign buf2_ff = buf_ff[2];
Line 566... Line 560...
wire [31:0] dbg_addr_tag = i_address[`VA__CACHE_TAG];
wire [31:0] dbg_addr_tag = i_address[`VA__CACHE_TAG];
wire [31:0] dbg_addr_pa  = i_phy_addr >> 4;
wire [31:0] dbg_addr_pa  = i_phy_addr >> 4;
wire [31:0] dbg_ct_tag   = o_cache_tag[`CACHE_TAG__TAG];
wire [31:0] dbg_ct_tag   = o_cache_tag[`CACHE_TAG__TAG];
wire [31:0] dbg_ct_pa    = o_cache_tag[`CACHE_TAG__PA];
wire [31:0] dbg_ct_pa    = o_cache_tag[`CACHE_TAG__PA];
 
 
// synopsys translate_on
 
 
 
endmodule // zap_cache_fsm
endmodule // zap_cache_fsm
 
 
`default_nettype wire
`default_nettype wire
 
 
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// ----------------------------------------------------------------------------
 
// END OF FILE
 
// ----------------------------------------------------------------------------
 
 
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