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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_cache_tag_ram.v] - Diff between revs 26 and 43

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Line 29... Line 29...
// -- depending on the cache controller.                                      --
// -- depending on the cache controller.                                      --
// --                                                                         --
// --                                                                         --
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
 
 
`default_nettype none
`default_nettype none
 
`include "zap_defines.vh"
 
 
module zap_cache_tag_ram ( // Verilog 1995 port syntax. Need to convert to 2001.
module zap_cache_tag_ram #(
 
 
i_clk,
 
i_reset,
 
 
 
i_address_nxt,
 
i_address,
 
 
 
i_cache_en,
 
 
 
i_cache_line,
 
o_cache_line,
 
 
 
i_cache_line_ben,
 
 
 
i_cache_tag_wr_en,
 
i_cache_tag,
 
i_cache_tag_dirty,
 
 
 
o_cache_tag,
 
o_cache_tag_valid,
 
o_cache_tag_dirty,
 
 
 
i_cache_inv_req,
parameter CACHE_SIZE = 1024 // Bytes.
o_cache_inv_done,
 
 
 
i_cache_clean_req,
)(
o_cache_clean_done,
 
 
 
// Cache clean operations occur through these ports.
input   wire                            i_clk,
o_wb_stb_nxt, o_wb_stb_ff,
input   wire                            i_reset,
o_wb_cyc_nxt, o_wb_cyc_ff,
input   wire    [31:0]                  i_address_nxt,
o_wb_adr_nxt, o_wb_adr_ff,
input   wire    [31:0]                  i_address,
o_wb_wen_nxt, o_wb_wen_ff,
input   wire                            i_cache_en,
o_wb_sel_nxt, o_wb_sel_ff,
input   wire    [127:0]                 i_cache_line,
o_wb_dat_nxt, o_wb_dat_ff,
input   wire    [15:0]                  i_cache_line_ben,
o_wb_cti_nxt, o_wb_cti_ff,
output  reg     [127:0]                 o_cache_line,
i_wb_ack, i_wb_dat
input   wire                            i_cache_tag_wr_en,
 
input   wire    [`CACHE_TAG_WDT-1:0]    i_cache_tag,
 
input   wire                            i_cache_tag_dirty,
 
 
 
output  reg     [`CACHE_TAG_WDT-1:0]    o_cache_tag,
 
output  reg                             o_cache_tag_valid,
 
output  reg                             o_cache_tag_dirty,
 
input   wire                            i_cache_clean_req,
 
output  reg                             o_cache_clean_done,
 
input   wire                            i_cache_inv_req,
 
output  reg                             o_cache_inv_done,
 
 
 
/*
 
 * Cache clean operations occur through these ports.
 
 * Memory access ports, both NXT and FF. Usually you'll be connecting NXT ports
 
 */
 
output  reg                             o_wb_cyc_ff, o_wb_cyc_nxt,
 
output  reg                             o_wb_stb_ff, o_wb_stb_nxt,
 
output  reg     [31:0]                  o_wb_adr_ff, o_wb_adr_nxt,
 
output  reg     [31:0]                  o_wb_dat_ff, o_wb_dat_nxt,
 
output  reg     [3:0]                   o_wb_sel_ff, o_wb_sel_nxt,
 
output  reg                             o_wb_wen_ff, o_wb_wen_nxt,
 
output  reg     [2:0]                   o_wb_cti_ff, o_wb_cti_nxt, /* Cycle Type Indicator - 010, 111 */
 
input wire      [31:0]                  i_wb_dat,
 
input wire                              i_wb_ack
 
 
);
);
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
`include "zap_localparams.vh"
`include "zap_localparams.vh"
`include "zap_defines.vh"
 
 
 
parameter CACHE_SIZE = 1024; // Bytes.
 
 
 
input   wire                            i_clk;
 
input   wire                            i_reset;
 
 
 
input   wire    [31:0]                  i_address_nxt;
localparam NUMBER_OF_DIRTY_BLOCKS = ((CACHE_SIZE/16)/16); // Keep cache size > 16 bytes.
input   wire    [31:0]                  i_address;
 
 
 
input   wire                            i_cache_en;
 
 
 
input   wire    [127:0]                 i_cache_line;
 
input   wire    [15:0]                  i_cache_line_ben;
 
output  reg     [127:0]                 o_cache_line;
 
 
 
input   wire                            i_cache_tag_wr_en;
 
input   wire    [`CACHE_TAG_WDT-1:0]    i_cache_tag;
 
input   wire                            i_cache_tag_dirty;
 
 
 
output  reg     [`CACHE_TAG_WDT-1:0]    o_cache_tag;
 
output  reg                             o_cache_tag_valid;
 
output  reg                             o_cache_tag_dirty;
 
 
 
input   wire                            i_cache_clean_req;
 
output  reg                             o_cache_clean_done;
 
 
 
input   wire                            i_cache_inv_req;
 
output  reg                             o_cache_inv_done;
 
 
 
/* Memory access ports, both NXT and FF. Usually you'll be connecting NXT ports */
 
output  reg                             o_wb_cyc_ff, o_wb_cyc_nxt;
 
output  reg                             o_wb_stb_ff, o_wb_stb_nxt;
 
output  reg     [31:0]                  o_wb_adr_ff, o_wb_adr_nxt;
 
output  reg     [31:0]                  o_wb_dat_ff, o_wb_dat_nxt;
 
output  reg     [3:0]                   o_wb_sel_ff, o_wb_sel_nxt;
 
output  reg                             o_wb_wen_ff, o_wb_wen_nxt;
 
output  reg     [2:0]                   o_wb_cti_ff, o_wb_cti_nxt; /* Cycle Type Indicator - 010, 111 */
 
input wire      [31:0]                  i_wb_dat;
 
input wire                              i_wb_ack;
 
 
 
// ----------------------------------------------------------------------------
// States.
 
localparam IDLE                         = 0;
 
localparam CACHE_CLEAN_GET_ADDRESS      = 1;
 
localparam CACHE_CLEAN_WRITE            = 2;
 
localparam CACHE_INV                    = 3;
 
 
localparam NUMBER_OF_DIRTY_BLOCKS = ((CACHE_SIZE/16)/16); // Keep cache size > 16 bytes.
 
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
reg [(CACHE_SIZE/16)-1:0]       dirty;
reg [(CACHE_SIZE/16)-1:0]       dirty;
reg [(CACHE_SIZE/16)-1:0]       valid;
reg [(CACHE_SIZE/16)-1:0]       valid;
Line 136... Line 103...
reg                             tag_ram_clear;
reg                             tag_ram_clear;
reg                             tag_ram_clean;
reg                             tag_ram_clean;
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
 
reg [1:0] state_ff, state_nxt;
 
 
 
// ----------------------------------------------------------------------------
 
 
reg [$clog2(NUMBER_OF_DIRTY_BLOCKS)-1:0] blk_ctr_ff, blk_ctr_nxt;
reg [$clog2(NUMBER_OF_DIRTY_BLOCKS)-1:0] blk_ctr_ff, blk_ctr_nxt;
reg [2:0] adr_ctr_ff, adr_ctr_nxt;
reg [2:0] adr_ctr_ff, adr_ctr_nxt;
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
initial
initial
begin: blk1
begin: blk1
 
        // FPGA anyway initializes to 0 on start.
        integer i;
        integer i;
 
 
        for(i=0;i<CACHE_SIZE/16;i=i+1)
        for(i=0;i<CACHE_SIZE/16;i=i+1)
                dat_ram[i] = 0;
                dat_ram[i] = 0;
 
 
Line 192... Line 164...
                o_cache_tag                 <= tag_ram [ tag_ram_rd_addr ];
                o_cache_tag                 <= tag_ram [ tag_ram_rd_addr ];
end
end
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
//integer i;
 
 
 
always @ (posedge i_clk)
always @ (posedge i_clk)
begin
begin
        o_cache_tag_dirty                   <= dirty [ tag_ram_rd_addr ];
        o_cache_tag_dirty                   <= dirty [ tag_ram_rd_addr ];
 
 
        if ( i_reset )
        if ( i_reset )
Line 218... Line 188...
                valid [ tag_ram_wr_addr ]   <= 1'd1;
                valid [ tag_ram_wr_addr ]   <= 1'd1;
end
end
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
localparam IDLE                         = 0;
 
localparam CACHE_CLEAN_GET_ADDRESS      = 1;
 
localparam CACHE_CLEAN_WRITE            = 2;
 
localparam CACHE_INV                    = 3;
 
 
 
reg [1:0] state_ff, state_nxt;
 
 
 
always @ (posedge i_clk)
always @ (posedge i_clk)
begin
begin
        if ( i_reset )
        if ( i_reset )
        begin
        begin
                o_wb_cyc_ff <= 0;
                o_wb_cyc_ff <= 0;
Line 257... Line 220...
        end
        end
end
end
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
 
 
 
 
function [4:0] baggage ( input [CACHE_SIZE/16-1:0] dirty, input [31:0] blk_ctr_ff );
 
reg [31:0] shamt;
 
integer i;
 
begin
 
        shamt = blk_ctr_ff << 4;
 
        baggage = pri_enc1(dirty >> shamt);
 
end
 
endfunction
 
 
 
always @*
always @*
begin
begin
 
 
        // Defaults.
        // Defaults.
        state_nxt = state_ff;
        state_nxt = state_ff;
Line 311... Line 263...
                if ( i_cache_clean_req )
                if ( i_cache_clean_req )
                begin
                begin
                        tag_ram_wr_en = 0;
                        tag_ram_wr_en = 0;
                        blk_ctr_nxt = 0;
                        blk_ctr_nxt = 0;
 
 
                `ifndef SYNTHESIS
                // assertions_start
                        $display($time, "%m :: INFO :: Cache clean requested...");
 
 
                        $display($time, " - %m :: Cache clean requested...");
 
 
                        for(i=0;i<CACHE_SIZE/16;i=i+1)
                        for(i=0;i<CACHE_SIZE/16;i=i+1)
                        begin
                        begin
                                $display("Line %d : %x %d", i, dat_ram[i], dirty[i]);
                                $display($time, " - %m :: Line %d : %x %d", i, dat_ram[i], dirty[i]);
                        end
                        end
 
 
                        `ifdef CACHE_DEBUG
                // assertions_end
                                $stop;
 
                        `endif
 
                `endif
 
 
 
 
 
                        state_nxt = CACHE_CLEAN_GET_ADDRESS;
                        state_nxt = CACHE_CLEAN_GET_ADDRESS;
                end
                end
                else if ( i_cache_inv_req )
                else if ( i_cache_inv_req )
Line 401... Line 351...
        end
        end
 
 
        endcase
        endcase
end
end
 
 
 
// -----------------------------------------------------------------------------
 
 
// Priority encoder.
// Priority encoder.
function  [4:0] pri_enc1 ( input [15:0] in );
function  [4:0] pri_enc1 ( input [15:0] in );
begin: priEncFn
begin: priEncFn
                casez ( in )
                casez ( in )
                16'b0000_0000_0000_0001: pri_enc1 = 4'd0;
                16'b0000_0000_0000_0001: pri_enc1 = 4'd0;
Line 426... Line 378...
                default:                 pri_enc1 = 5'b11111;
                default:                 pri_enc1 = 5'b11111;
                endcase
                endcase
end
end
endfunction
endfunction
 
 
 
// -----------------------------------------------------------------------------
 
 
function [31:0] get_tag_ram_rd_addr (
function [31:0] get_tag_ram_rd_addr (
input [31:0] blk_ctr,
input [31:0] blk_ctr,
input [CACHE_SIZE/16-1:0] dirty
input [CACHE_SIZE/16-1:0] dirty
);
);
reg [CACHE_SIZE/16-1:0] dirty_new;
reg [CACHE_SIZE/16-1:0] dirty_new;
Line 448... Line 402...
/* Function to generate Wishbone read signals. */
/* Function to generate Wishbone read signals. */
task  wb_prpr_read;
task  wb_prpr_read;
input [31:0] i_address;
input [31:0] i_address;
input [2:0]  i_cti;
input [2:0]  i_cti;
begin
begin
        $display($time, "%m :: Reading from address %x", i_address);
        $display($time, " - %m :: Reading from address %x", i_address);
 
 
        o_wb_cyc_nxt = 1'd1;
        o_wb_cyc_nxt = 1'd1;
        o_wb_stb_nxt = 1'd1;
        o_wb_stb_nxt = 1'd1;
        o_wb_wen_nxt = 1'd0;
        o_wb_wen_nxt = 1'd0;
        o_wb_sel_nxt = 4'b1111;
        o_wb_sel_nxt = 4'b1111;
Line 496... Line 450...
end
end
endtask
endtask
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
 
function [4:0] baggage ( input [CACHE_SIZE/16-1:0] dirty, input [31:0] blk_ctr_ff );
 
reg [31:0] shamt;
 
integer i;
 
begin
 
        shamt = blk_ctr_ff << 4;
 
        baggage = pri_enc1(dirty >> shamt);
 
end
 
endfunction
 
 
endmodule // zap_cache_tag_ram.v
endmodule // zap_cache_tag_ram.v
`default_nettype wire
`default_nettype wire
 
 
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