OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_cache_tag_ram.v] - Diff between revs 43 and 51

Show entire file | Details | Blame | View Log

Rev 43 Rev 51
Line 24... Line 24...
// -- This is the tag RAM and data RAM unit. The tag RAM holds both the       --
// -- This is the tag RAM and data RAM unit. The tag RAM holds both the       --
// -- virtual tag and the physical address. The physical address is used to   --  
// -- virtual tag and the physical address. The physical address is used to   --  
// -- avoid translation during clean operations. The cache data RAM is also   --
// -- avoid translation during clean operations. The cache data RAM is also   --
// -- present in this unit. This unit has a dedicated memory interface        -- 
// -- present in this unit. This unit has a dedicated memory interface        -- 
// -- because it can perform global clean and flush by itself without         --
// -- because it can perform global clean and flush by itself without         --
// -- depending on the cache controller.                                      --
// -- depending on the cache controller. Only for FPGA.                       --
// --                                                                         --
// --                                                                         --
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
 
 
`default_nettype none
`default_nettype none
 
 
`include "zap_defines.vh"
`include "zap_defines.vh"
 
 
module zap_cache_tag_ram #(
module zap_cache_tag_ram #(
 
 
parameter CACHE_SIZE = 1024 // Bytes.
parameter CACHE_SIZE = 1024 // Bytes.
Line 263... Line 264...
                if ( i_cache_clean_req )
                if ( i_cache_clean_req )
                begin
                begin
                        tag_ram_wr_en = 0;
                        tag_ram_wr_en = 0;
                        blk_ctr_nxt = 0;
                        blk_ctr_nxt = 0;
 
 
                // assertions_start
 
 
 
                        $display($time, " - %m :: Cache clean requested...");
 
 
 
                        for(i=0;i<CACHE_SIZE/16;i=i+1)
 
                        begin
 
                                $display($time, " - %m :: Line %d : %x %d", i, dat_ram[i], dirty[i]);
 
                        end
 
 
 
                // assertions_end
 
 
 
 
 
                        state_nxt = CACHE_CLEAN_GET_ADDRESS;
                        state_nxt = CACHE_CLEAN_GET_ADDRESS;
                end
                end
                else if ( i_cache_inv_req )
                else if ( i_cache_inv_req )
                begin
                begin
                        tag_ram_wr_en = 0;
                        tag_ram_wr_en = 0;
Line 402... Line 391...
/* Function to generate Wishbone read signals. */
/* Function to generate Wishbone read signals. */
task  wb_prpr_read;
task  wb_prpr_read;
input [31:0] i_address;
input [31:0] i_address;
input [2:0]  i_cti;
input [2:0]  i_cti;
begin
begin
        $display($time, " - %m :: Reading from address %x", i_address);
 
 
 
        o_wb_cyc_nxt = 1'd1;
        o_wb_cyc_nxt = 1'd1;
        o_wb_stb_nxt = 1'd1;
        o_wb_stb_nxt = 1'd1;
        o_wb_wen_nxt = 1'd0;
        o_wb_wen_nxt = 1'd0;
        o_wb_sel_nxt = 4'b1111;
        o_wb_sel_nxt = 4'b1111;
        o_wb_adr_nxt = i_address;
        o_wb_adr_nxt = i_address;
Line 460... Line 447...
        baggage = pri_enc1(dirty >> shamt);
        baggage = pri_enc1(dirty >> shamt);
end
end
endfunction
endfunction
 
 
endmodule // zap_cache_tag_ram.v
endmodule // zap_cache_tag_ram.v
 
 
`default_nettype wire
`default_nettype wire
 
 
 No newline at end of file
 No newline at end of file
 
// ----------------------------------------------------------------------------
 
// END OF FILE
 
// ----------------------------------------------------------------------------
 
 
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.