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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_decode.v] - Diff between revs 26 and 37

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Rev 26 Rev 37
Line 125... Line 125...
localparam [1:0] SIGNED_HALF_WORD       = 2'd2;
localparam [1:0] SIGNED_HALF_WORD       = 2'd2;
 
 
`ifndef SYNTHESIS
`ifndef SYNTHESIS
 
 
// Debug only.
// Debug only.
reg bx, dp, br, mrs, msr, ls, mult, halfword_ls, swi, dp1, dp2, dp3, lmult;
reg bx, dp, br, mrs, msr, ls, mult, halfword_ls, swi, dp1, dp2, dp3, lmult, clz;
 
 
always @*
always @*
begin
begin
        bx  = 0;
        bx  = 0;
        dp  = 0;
        dp  = 0;
Line 147... Line 147...
        //
        //
        // Debugging purposes.
        // Debugging purposes.
        //
        //
        if ( i_instruction_valid )
        if ( i_instruction_valid )
        casez ( i_instruction[31:0] )
        casez ( i_instruction[31:0] )
 
        CLZ_INSTRUCTION:                               clz = 1;
        BX_INST:                                       bx  = 1;
        BX_INST:                                       bx  = 1;
        MRS:                                           mrs = 1;
        MRS:                                           mrs = 1;
        MSR,MSR_IMMEDIATE:                             msr = 1;
        MSR,MSR_IMMEDIATE:                             msr = 1;
        DATA_PROCESSING_IMMEDIATE,
        DATA_PROCESSING_IMMEDIATE,
        DATA_PROCESSING_REGISTER_SPECIFIED_SHIFT,
        DATA_PROCESSING_REGISTER_SPECIFIED_SHIFT,
Line 215... Line 216...
                        o_shift_length      = 0;
                        o_shift_length      = 0;
                        o_shift_length[32]  = IMMED_EN;
                        o_shift_length[32]  = IMMED_EN;
                end
                end
                else if ( i_instruction_valid )
                else if ( i_instruction_valid )
                casez ( i_instruction[31:0] )
                casez ( i_instruction[31:0] )
 
                CLZ_INSTRUCTION:              decode_clz ( i_instruction );
                BX_INST:                      decode_bx ( i_instruction );
                BX_INST:                      decode_bx ( i_instruction );
                MRS:                          decode_mrs ( i_instruction );
                MRS:                          decode_mrs ( i_instruction );
                MSR,MSR_IMMEDIATE:            decode_msr ( i_instruction );
                MSR,MSR_IMMEDIATE:            decode_msr ( i_instruction );
 
 
                DATA_PROCESSING_IMMEDIATE,
                DATA_PROCESSING_IMMEDIATE,
Line 244... Line 246...
end
end
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
// =============================
// =============================
 
// Decode CLZ
 
// =============================
 
task decode_clz ( input [35:0] i_instruction );
 
begin: tskDecodeClz
 
        o_condition_code        =       i_instruction[31:28];
 
        o_flag_update           =       1'd0; // Instruction does not update any flags.
 
        o_alu_operation         =       CLZ;  // Added.
 
 
 
        // Rn = 0.
 
        o_alu_source            =       0;
 
        o_alu_source[32]        =       IMMED_EN;
 
 
 
        // Rm = register whose CLZ must be found.
 
        o_shift_source          =       {i_instruction[`DP_RB_EXTEND], i_instruction[`DP_RB]}; // Rm
 
        o_shift_source[32]      =       INDEX_EN;
 
        o_shift_operation       =       LSL;
 
        o_shift_length          =       0;
 
        o_shift_length[32]      =       IMMED_EN; // Shift length is 0 of course.
 
end
 
endtask
 
 
 
// =============================
// Decode long multiplication.
// Decode long multiplication.
// =============================
// =============================
task decode_lmult ( input [35:0] i_instruction ); // Uses bit 35. rm.rs + {rh, rn}
task decode_lmult ( input [35:0] i_instruction ); // Uses bit 35. rm.rs + {rh, rn}
begin: tskLDecodeMult
begin: tskLDecodeMult
 
 
Line 469... Line 493...
// =============================
// =============================
// Converted into a MOV to PC. The task of setting the T-bit in the CPSR is
// Converted into a MOV to PC. The task of setting the T-bit in the CPSR is
// the job of the writeback stage.
// the job of the writeback stage.
task decode_bx( input [34:0] i_instruction );
task decode_bx( input [34:0] i_instruction );
begin: tskDecodeBx
begin: tskDecodeBx
        reg [31:0] temp;
        reg [34:0] temp;
 
 
        temp = i_instruction[31:0];
        temp = i_instruction[31:0];
        temp[11:4] = 0;
        temp[31:4] = 0; // Zero out stuff to avoid conflicts in the function.
 
 
        process_instruction_specified_shift(temp[11:0]);
        process_instruction_specified_shift(temp);
 
 
        // The RAW ALU source does not matter.
        // The RAW ALU source does not matter.
        o_condition_code        = i_instruction[31:28];
        o_condition_code        = i_instruction[31:28];
        o_alu_operation         = MOV;
        o_alu_operation         = MOV;
        o_destination_index     = ARCH_PC;
        o_destination_index     = ARCH_PC;

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