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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_decode.v] - Diff between revs 37 and 43

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Rev 37 Rev 43
Line 122... Line 122...
// Related to memory operations.
// Related to memory operations.
localparam [1:0] SIGNED_BYTE            = 2'd0;
localparam [1:0] SIGNED_BYTE            = 2'd0;
localparam [1:0] UNSIGNED_HALF_WORD     = 2'd1;
localparam [1:0] UNSIGNED_HALF_WORD     = 2'd1;
localparam [1:0] SIGNED_HALF_WORD       = 2'd2;
localparam [1:0] SIGNED_HALF_WORD       = 2'd2;
 
 
`ifndef SYNTHESIS
// assertions_start
 
 
// Debug only.
// Debug only.
reg bx, dp, br, mrs, msr, ls, mult, halfword_ls, swi, dp1, dp2, dp3, lmult, clz;
reg bx, dp, br, mrs, msr, ls, mult, halfword_ls, swi, dp1, dp2, dp3, lmult, clz;
 
 
always @*
always @*
Line 169... Line 169...
        HALFWORD_LS:                      halfword_ls     = 1;
        HALFWORD_LS:                      halfword_ls     = 1;
        SOFTWARE_INTERRUPT:               swi             = 1;
        SOFTWARE_INTERRUPT:               swi             = 1;
        endcase
        endcase
end
end
 
 
`endif
// assertions_end
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
always @*
always @*
begin: mainBlk1
begin: mainBlk1
Line 691... Line 691...
// If an immediate value is to be rotated right by an 
// If an immediate value is to be rotated right by an 
// immediate value, this mode is used.
// immediate value, this mode is used.
//
//
task process_immediate ( input [34:0] instruction );
task process_immediate ( input [34:0] instruction );
begin
begin
        `ifndef SYNTHESIS
 
                dp1 = 1;
                dp1 = 1;
        `endif
 
 
 
        o_shift_length          = instruction[11:8] << 1'd1;
        o_shift_length          = instruction[11:8] << 1'd1;
        o_shift_length[32]      = IMMED_EN;
        o_shift_length[32]      = IMMED_EN;
        o_shift_source          = instruction[7:0];
        o_shift_source          = instruction[7:0];
        o_shift_source[32]      = IMMED_EN;
        o_shift_source[32]      = IMMED_EN;
Line 711... Line 709...
// The shifter source is a register but the 
// The shifter source is a register but the 
// amount to shift is in the instruction itself.
// amount to shift is in the instruction itself.
//
//
task process_instruction_specified_shift ( input [34:0] instruction );
task process_instruction_specified_shift ( input [34:0] instruction );
begin
begin
        `ifndef SYNTHESIS
 
                dp2 = 1;
                dp2 = 1;
        `endif
 
 
 
        // ROR #0 = RRC, ASR #0 = ASR #32, LSL #0 = LSL #0, LSR #0 = LSR #32 
        // ROR #0 = RRC, ASR #0 = ASR #32, LSL #0 = LSL #0, LSR #0 = LSR #32 
        // ROR #n = ROR_1 #n ( n > 0 )
        // ROR #n = ROR_1 #n ( n > 0 )
        o_shift_length          = instruction[11:7];
        o_shift_length          = instruction[11:7];
        o_shift_length[32]      = IMMED_EN;
        o_shift_length[32]      = IMMED_EN;
Line 753... Line 749...
begin
begin
`ifdef DECODE_DEBUG
`ifdef DECODE_DEBUG
        $display("%m Process register specified shift...");
        $display("%m Process register specified shift...");
`endif
`endif
 
 
        `ifndef SYNTHESIS
 
                dp3 = 1;
                dp3 = 1;
        `endif
 
 
 
        o_shift_length          = instruction[11:8];
        o_shift_length          = instruction[11:8];
        o_shift_length[32]      = INDEX_EN;
        o_shift_length[32]      = INDEX_EN;
        o_shift_source          = {i_instruction[`DP_RB_EXTEND], instruction[`DP_RB]};
        o_shift_source          = {i_instruction[`DP_RB_EXTEND], instruction[`DP_RB]};
        o_shift_source[32]      = INDEX_EN;
        o_shift_source[32]      = INDEX_EN;

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