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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_decode.v] - Diff between revs 46 and 51

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Line 122... Line 122...
// Related to memory operations.
// Related to memory operations.
localparam [1:0] SIGNED_BYTE            = 2'd0;
localparam [1:0] SIGNED_BYTE            = 2'd0;
localparam [1:0] UNSIGNED_HALF_WORD     = 2'd1;
localparam [1:0] UNSIGNED_HALF_WORD     = 2'd1;
localparam [1:0] SIGNED_HALF_WORD       = 2'd2;
localparam [1:0] SIGNED_HALF_WORD       = 2'd2;
 
 
// assertions_start
 
 
 
        // Debug only.
 
        reg bx, dp, br, mrs, msr, ls, mult, halfword_ls, swi, dp1, dp2, dp3, lmult, clz;
 
 
 
        always @*
 
        begin
 
                bx      = 0;
 
                dp      = 0;
 
                br      = 0;
 
                mrs     = 0;
 
                msr     = 0;
 
                ls      = 0;
 
                mult    = 0;
 
                halfword_ls = 0;
 
                swi = 0;
 
                dp1 = 0;
 
                dp2 = 0;
 
                dp3 = 0;
 
 
 
                //
 
                // Debugging purposes.
 
                //
 
                if ( i_instruction_valid )
 
                casez ( i_instruction[31:0] )
 
                CLZ_INSTRUCTION:                               clz = 1;
 
                BX_INST:                                       bx  = 1;
 
                MRS:                                           mrs = 1;
 
                MSR,MSR_IMMEDIATE:                             msr = 1;
 
                DATA_PROCESSING_IMMEDIATE,
 
                DATA_PROCESSING_REGISTER_SPECIFIED_SHIFT,
 
                DATA_PROCESSING_INSTRUCTION_SPECIFIED_SHIFT:   dp  = 1;
 
                BRANCH_INSTRUCTION:                            br  = 1;
 
                LS_INSTRUCTION_SPECIFIED_SHIFT,LS_IMMEDIATE:
 
                begin
 
                        if ( i_instruction[20] )
 
                                ls  = 1; // Load
 
                        else
 
                                ls  = 2;  // Store
 
                end
 
                MULT_INST:                        mult            = 1;
 
                LMULT_INST:                       lmult           = 1;
 
                HALFWORD_LS:                      halfword_ls     = 1;
 
                SOFTWARE_INTERRUPT:               swi             = 1;
 
                endcase
 
        end
 
 
 
// assertions_end
 
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
always @*
always @*
begin: mainBlk1
begin: mainBlk1
        // If an unrecognized instruction enters this, the output
        // If an unrecognized instruction enters this, the output
Line 296... Line 247...
                                        {i_instruction[`DP_RA_EXTEND],
                                        {i_instruction[`DP_RA_EXTEND],
                                         i_instruction[`DP_RD]} : 32'd0;
                                         i_instruction[`DP_RD]} : 32'd0;
 
 
        o_shift_length[32]      =       i_instruction[24] ? INDEX_EN:IMMED_EN;
        o_shift_length[32]      =       i_instruction[24] ? INDEX_EN:IMMED_EN;
 
 
`ifdef DECODE_DEBUG
 
        $display($time, "Long multiplication detected!");
 
`endif
 
 
 
        // We need to generate output code.
        // We need to generate output code.
        case ( i_instruction[22:21] )
        case ( i_instruction[22:21] )
        2'b00:
        2'b00:
        begin
        begin
Line 454... Line 402...
// Decode short multiplication.
// Decode short multiplication.
// ==============================
// ==============================
task decode_mult( input [34:0] i_instruction );
task decode_mult( input [34:0] i_instruction );
begin: tskDecodeMult
begin: tskDecodeMult
 
 
`ifdef DECODE_DEBUG
 
        $display($time, "%m: MLT 32x32 -> 32 decode...");
 
`endif
 
 
 
        o_condition_code        =       i_instruction[31:28];
        o_condition_code        =       i_instruction[31:28];
        o_flag_update           =       i_instruction[20];
        o_flag_update           =       i_instruction[20];
        o_alu_operation         =       UMLALL;
        o_alu_operation         =       UMLALL;
        o_destination_index     =       {i_instruction[`DP_RD_EXTEND],
        o_destination_index     =       {i_instruction[`DP_RD_EXTEND],
Line 522... Line 467...
// Task for decoding load-store instructions.
// Task for decoding load-store instructions.
// =============================================
// =============================================
task decode_ls( input [34:0] i_instruction );
task decode_ls( input [34:0] i_instruction );
begin: tskDecodeLs
begin: tskDecodeLs
 
 
`ifdef DECODE_DEBUG
 
        $display($time, "%m: LS decode...");
 
`endif
 
 
 
        o_condition_code = i_instruction[31:28];
        o_condition_code = i_instruction[31:28];
 
 
        if ( !i_instruction[25] ) // immediate
        if ( !i_instruction[25] ) // immediate
        begin
        begin
Line 688... Line 630...
// If an immediate value is to be rotated right by an 
// If an immediate value is to be rotated right by an 
// immediate value, this mode is used.
// immediate value, this mode is used.
//
//
task process_immediate ( input [34:0] instruction );
task process_immediate ( input [34:0] instruction );
begin
begin
        dp1 = 1;
 
 
 
        o_shift_length          = instruction[11:8] << 1'd1;
        o_shift_length          = instruction[11:8] << 1'd1;
        o_shift_length[32]      = IMMED_EN;
        o_shift_length[32]      = IMMED_EN;
        o_shift_source          = instruction[7:0];
        o_shift_source          = instruction[7:0];
        o_shift_source[32]      = IMMED_EN;
        o_shift_source[32]      = IMMED_EN;
        o_shift_operation       = RORI;
        o_shift_operation       = RORI;
Line 706... Line 646...
// The shifter source is a register but the 
// The shifter source is a register but the 
// amount to shift is in the instruction itself.
// amount to shift is in the instruction itself.
//
//
task process_instruction_specified_shift ( input [34:0] instruction );
task process_instruction_specified_shift ( input [34:0] instruction );
begin
begin
         dp2 = 1;
 
 
 
        // ROR #0 = RRC, ASR #0 = ASR #32, LSL #0 = LSL #0, LSR #0 = LSR #32 
        // ROR #0 = RRC, ASR #0 = ASR #32, LSL #0 = LSL #0, LSR #0 = LSR #32 
        // ROR #n = ROR_1 #n ( n > 0 )
        // ROR #n = ROR_1 #n ( n > 0 )
        o_shift_length          = instruction[11:7];
        o_shift_length          = instruction[11:7];
        o_shift_length[32]      = IMMED_EN;
        o_shift_length[32]      = IMMED_EN;
        o_shift_source          = {i_instruction[`DP_RB_EXTEND],instruction[`DP_RB]};
        o_shift_source          = {i_instruction[`DP_RB_EXTEND],instruction[`DP_RB]};
Line 742... Line 680...
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
// The source register and the amount of shift are both in registers.
// The source register and the amount of shift are both in registers.
task process_register_specified_shift ( input [34:0] instruction );
task process_register_specified_shift ( input [34:0] instruction );
begin
begin
`ifdef DECODE_DEBUG
 
        $display("%m Process register specified shift...");
 
`endif
 
 
 
        dp3 = 1;
 
 
 
        o_shift_length          = instruction[11:8];
        o_shift_length          = instruction[11:8];
        o_shift_length[32]      = INDEX_EN;
        o_shift_length[32]      = INDEX_EN;
        o_shift_source          = {i_instruction[`DP_RB_EXTEND], instruction[`DP_RB]};
        o_shift_source          = {i_instruction[`DP_RB_EXTEND], instruction[`DP_RB]};
        o_shift_source[32]      = INDEX_EN;
        o_shift_source[32]      = INDEX_EN;
        o_shift_operation       = instruction[6:5];
        o_shift_operation       = instruction[6:5];

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