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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_decompile.v] - Diff between revs 39 and 43

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Rev 39 Rev 43
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// ---------------------------------------------------------------------------
// ---------------------------------------------------------------------------
 
 
`default_nettype none
`default_nettype none
 
 
module zap_decompile #(parameter INS_WDT = 36) (
module zap_decompile #(parameter INS_WDT = 36) (
                input wire      [36-1:0]        i_instruction,  // 36-bit instruction.
                input wire      [36-1:0]        i_instruction,  // 36-bit instruction into decode.
                input wire                      i_dav,          // Instruction valid.
                input wire                      i_dav,          // Instruction valid.
                output reg      [64*8-1:0]      o_decompile     // 1024 bytes max of assembler string.
                output reg      [64*8-1:0]      o_decompile     // 1024 bytes max of assembler string.
        );
        );
 
 
`ifndef SYNTHESIS // if simulating...
`ifndef SYNTHESIS
 
 
`include "zap_defines.vh"
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
`include "zap_functions.vh"
 
 
 
`ifndef ZAP_DECOMPILE_DEFINES
// These defines can be wrapped around a single `ifndef instead of several of
 
// them as shown.
 
 
 
`ifndef CCC
 
        `define CCC cond_code(i_instruction[31:28])
        `define CCC cond_code(i_instruction[31:28])
`endif
 
 
 
`ifndef CRB
 
        `define CRB arch_reg_num({i_instruction[`DP_RB_EXTEND], i_instruction[`DP_RB]})
        `define CRB arch_reg_num({i_instruction[`DP_RB_EXTEND], i_instruction[`DP_RB]})
`endif
 
 
 
`ifndef CRD
 
        `define CRD arch_reg_num({i_instruction[`DP_RD_EXTEND], i_instruction[`DP_RD]})
        `define CRD arch_reg_num({i_instruction[`DP_RD_EXTEND], i_instruction[`DP_RD]})
`endif
 
 
 
`ifndef CDR1
 
        `define CRD1 arch_reg_num({i_instruction[`SRCDEST_EXTEND], i_instruction[`SRCDEST]})
        `define CRD1 arch_reg_num({i_instruction[`SRCDEST_EXTEND], i_instruction[`SRCDEST]})
`endif
 
 
 
`ifndef CRN
 
        `define CRN arch_reg_num({i_instruction[`DP_RA_EXTEND], i_instruction[`DP_RA]})
        `define CRN arch_reg_num({i_instruction[`DP_RA_EXTEND], i_instruction[`DP_RA]})
`endif
 
 
 
`ifndef CRN1
 
        `define CRN1 arch_reg_num({i_instruction[`BASE_EXTEND], i_instruction[`BASE]})
        `define CRN1 arch_reg_num({i_instruction[`BASE_EXTEND], i_instruction[`BASE]})
`endif
 
 
 
`ifndef COPCODE
 
        `define COPCODE get_opcode({i_instruction[`OPCODE_EXTEND], i_instruction[24:21]})
        `define COPCODE get_opcode({i_instruction[`OPCODE_EXTEND], i_instruction[24:21]})
`endif
 
 
 
`ifndef CSHTYPE
 
        `define CSHTYPE get_shtype(i_instruction[6:5])
        `define CSHTYPE get_shtype(i_instruction[6:5])
`endif
 
 
 
`ifndef CRS
 
        `define CRS arch_reg_num(i_instruction[11:8]);
        `define CRS arch_reg_num(i_instruction[11:8]);
`endif
 
 
 
`ifndef CRM
 
        `define CRM arch_reg_num({i_instruction[`DP_RB_EXTEND], i_instruction[`DP_RB]});
        `define CRM arch_reg_num({i_instruction[`DP_RB_EXTEND], i_instruction[`DP_RB]});
`endif
`endif
 
 
// Decompile block. Makes task calls.
 
always @*
always @*
begin
begin
                if ( !i_dav )
                if ( !i_dav )
                begin
                begin
                        o_decompile = "IGNORE";
                        o_decompile = "IGNORE";
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end
end
endfunction
endfunction
 
 
`else
`else
 
 
// `ifdef SYNTHESIS
 
always @*
always @*
        o_decompile = 0; // In synthesis mode.
        o_decompile = 0; // In synthesis mode.
 
 
`endif
`endif
 
 

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