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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_fetch_main.v] - Diff between revs 39 and 43

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Rev 39 Rev 43
Line 75... Line 75...
 
 
// For BP.
// For BP.
input wire         i_confirm_from_alu,  // Confirm branch prediction from ALU.
input wire         i_confirm_from_alu,  // Confirm branch prediction from ALU.
input wire [31:0]  i_pc_from_alu,       // Address of branch. 
input wire [31:0]  i_pc_from_alu,       // Address of branch. 
input wire [1:0]   i_taken,             // Predicted status.
input wire [1:0]   i_taken,             // Predicted status.
output wire [1:0]  o_taken_ff           // Prediction. Not a flip-flop...
output wire [1:0]  o_taken              // Prediction. Not a flip-flop...
 
 
);
);
 
 
`include "zap_defines.vh"
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_localparams.vh"
Line 93... Line 93...
 
 
// Taken_v
// Taken_v
wire [1:0] taken_v;
wire [1:0] taken_v;
 
 
// Predict non branches as not taken...
// Predict non branches as not taken...
assign o_taken_ff = i_instruction[28:26] == 3'b101 ? taken_v : SNT;
assign o_taken    = o_instruction[28:26] == 3'b101 ? taken_v : SNT;
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
//
//
// This is the instruction payload on an abort
// This is the instruction payload on an abort
Line 188... Line 188...
                // Invalidate the output.
                // Invalidate the output.
                o_valid        <= 1'd0;
                o_valid        <= 1'd0;
        end
        end
end
end
 
 
`ifndef SYNTHESIS
 
 
 
always @ (negedge i_clk)
always @ (negedge i_clk)
begin
begin
        if ( i_pc_ff[0] != 1'd0 )
        if ( i_pc_ff[0] != 1'd0 )
        begin
        begin
                $display($time, ": Error: PC LSB isn't zero. This is not legal! (Module_Src = %m)");
                $display($time, " - %m :: Error: PC LSB isn't zero. This is not legal...");
                $finish;
                $finish;
        end
        end
end
end
 
 
`endif
 
 
 
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
 
 
//
//
// Branch State RAM.
// Branch State RAM.
// Holds the 2-bit state for a range of branches. Whenever a branch is
// Holds the 2-bit state for a range of branches. Whenever a branch is
Line 299... Line 295...
assign _unused_ok_ =   i_pc_from_alu[0] &&
assign _unused_ok_ =   i_pc_from_alu[0] &&
                       i_pc_from_alu[31:$clog2(BP_ENTRIES) + 1];
                       i_pc_from_alu[31:$clog2(BP_ENTRIES) + 1];
 
 
// ---------------------------------------------------------------------------------
// ---------------------------------------------------------------------------------
 
 
`ifndef SYNTHESIS
 
 
 
zap_decompile u_zap_decompile (
zap_decompile u_zap_decompile (
        .i_instruction  ({4'd0, o_instruction}),
        .i_instruction  ({4'd0, o_instruction}),
        .i_dav          (o_valid),
        .i_dav          (o_valid),
        .o_decompile    ()
        .o_decompile    ()
);
);
 
 
`endif
 
 
 
endmodule // zap_fetch_main.v
endmodule // zap_fetch_main.v
`default_nettype wire
`default_nettype wire
 
 
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