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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_issue_main.v] - Diff between revs 26 and 41

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// ----------------------------------------------------------------------------
// ---------------------------------------------------------------------------
//                            The ZAP Project
// --                                                                       --
//                     (C)2016-2017, Revanth Kamaraj.     
// --                   (C) 2016-2018 Revanth Kamaraj.                      --
// ----------------------------------------------------------------------------
// --                                                                       -- 
// Filename     : zap_issue_main.v
// -- ------------------------------------------------------------------------
// HDL          : Verilog-2001
// --                                                                       --
// Module       : zap_issue       
// -- This program is free software; you can redistribute it and/or         --
// Author       : Revanth Kamaraj
// -- modify it under the terms of the GNU General Public License           --
// License      : GPL v2
// -- as published by the Free Software Foundation; either version 2        --
// ----------------------------------------------------------------------------
// -- of the License, or (at your option) any later version.                --
//                               ABSTRACT
// --                                                                       --
//                               --------
// -- This program is distributed in the hope that it will be useful,       --
 
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of        --
 
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         --
 
// -- GNU General Public License for more details.                          --
 
// --                                                                       --
 
// -- You should have received a copy of the GNU General Public License     --
 
// -- along with this program; if not, write to the Free Software           --
 
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA         --
 
// -- 02110-1301, USA.                                                      --
 
// --                                                                       --
 
// ---------------------------------------------------------------------------
//  This stage converts register indices into actual values. Register indices
//  This stage converts register indices into actual values. Register indices
//  are also pumped forward to allow resolution in the shift stage. PC
//  are also pumped forward to allow resolution in the shift stage. PC
//  references must be resolved here since the value gives PC + 8. Instructions
//  references must be resolved here since the value gives PC + 8. Instructions
//  requiring shifts stall if the target registers are in the outputs of this
//  requiring shifts stall if the target registers are in the outputs of this
//  stage. We do not issue a multiply if the source is still in the output of this 
//  stage. We do not issue a multiply if the source is still in the output of this 
//  stage just like shifts. That's to ensure incorrect registers are not
//  stage just like shifts. That's to ensure incorrect registers are not
//  read.
//  read.
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
//                              INFORMATION                                  
 
//                              ------------
 
// Reset method : Synchronous active high reset
 
// Clock        : Core clock
 
// Depends      : --        
 
// ----------------------------------------------------------------------------
 
 
 
`default_nettype none
`default_nettype none
 
 
module zap_issue_main
module zap_issue_main
#(
#(

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