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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_ram_simple.v] - Diff between revs 26 and 51

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Rev 26 Rev 51
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// -- 02110-1301, USA.                                                        --
// -- 02110-1301, USA.                                                        --
// --                                                                         --
// --                                                                         --
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// --                                                                         -- 
// --                                                                         -- 
// --  Synthesizes to standard 1R + 1W block RAM. The read and write addresses--
// --  Synthesizes to standard 1R + 1W block RAM. The read and write addresses--
// --  may be specified separately.                                           --
// --  may be specified separately. Only for FPGA.                            --
// --                                                                         --
// --                                                                         --
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
 
 
`default_nettype none
`default_nettype none
 
 
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        if ( i_wr_en )
        if ( i_wr_en )
                mem [ i_wr_addr ] <= i_wr_data;
                mem [ i_wr_addr ] <= i_wr_data;
end
end
 
 
endmodule // ram_simple.v
endmodule // ram_simple.v
 
 
`default_nettype wire
`default_nettype wire
 
 
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// ----------------------------------------------------------------------------
 
// EOF
 
// ----------------------------------------------------------------------------
 
 
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