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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_register_file.v] - Diff between revs 26 and 43

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Rev 26 Rev 43
Line 68... Line 68...
        end
        end
end
end
 
 
reg [39:0] sel;
reg [39:0] sel;
 
 
`ifndef SYNTHESIS
// assertions_start
        wire [31:0] r0;  assign r0 =  sel[0]  ? MEM[0] : mem[0];
        wire [31:0] r0;  assign r0 =  sel[0]  ? MEM[0] : mem[0];
        wire [31:0] r1;  assign r1 =  sel[1]  ? MEM[1] : mem[1];
        wire [31:0] r1;  assign r1 =  sel[1]  ? MEM[1] : mem[1];
        wire [31:0] r2;  assign r2 =  sel[2]  ? MEM[2] : mem[2];
        wire [31:0] r2;  assign r2 =  sel[2]  ? MEM[2] : mem[2];
        wire [31:0] r3;  assign r3 =  sel[3]  ? MEM[3] : mem[3];
        wire [31:0] r3;  assign r3 =  sel[3]  ? MEM[3] : mem[3];
        wire [31:0] r4;  assign r4 =  sel[4]  ? MEM[4] : mem[4];
        wire [31:0] r4;  assign r4 =  sel[4]  ? MEM[4] : mem[4];
Line 109... Line 109...
        wire [31:0] r35; assign r35 = sel[35] ? MEM[35] : mem[35];
        wire [31:0] r35; assign r35 = sel[35] ? MEM[35] : mem[35];
        wire [31:0] r36; assign r36 = sel[36] ? MEM[36] : mem[36];
        wire [31:0] r36; assign r36 = sel[36] ? MEM[36] : mem[36];
        wire [31:0] r37; assign r37 = sel[37] ? MEM[37] : mem[37];
        wire [31:0] r37; assign r37 = sel[37] ? MEM[37] : mem[37];
        wire [31:0] r38; assign r38 = sel[38] ? MEM[38] : mem[38];
        wire [31:0] r38; assign r38 = sel[38] ? MEM[38] : mem[38];
        wire [31:0] r39; assign r39 = sel[39] ? MEM[39] : mem[39];
        wire [31:0] r39; assign r39 = sel[39] ? MEM[39] : mem[39];
`endif
// assertions_end
 
 
always @ (posedge i_clk)
always @ (posedge i_clk)
begin
begin
        if ( i_reset )
        if ( i_reset )
        begin
        begin

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