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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_sync_fifo.v] - Diff between revs 26 and 43

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// -- along with this program; if not, write to the Free Software             --
// -- along with this program; if not, write to the Free Software             --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA           --
// -- 02110-1301, USA.                                                        --
// -- 02110-1301, USA.                                                        --
// --                                                                         --
// --                                                                         --
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
 
// -- This is a simple synchronous FIFO.                                      --
 
// -----------------------------------------------------------------------------
 
 
`default_nettype none
`default_nettype none
 
 
// FWFT means "First Word Fall Through".
// FWFT means "First Word Fall Through".
module zap_sync_fifo #(parameter WIDTH = 32, parameter DEPTH = 32, parameter FWFT = 1)
module zap_sync_fifo #(
 
        parameter WIDTH            = 32,
 
        parameter DEPTH            = 32,
 
        parameter FWFT             = 1,
 
        parameter PROVIDE_NXT_DATA = 0
 
)
(
(
 
        // Clock and reset
        input   wire             i_clk,
        input   wire             i_clk,
        input   wire             i_reset,
        input   wire             i_reset,
 
 
 
        // Flow control
        input   wire             i_ack,
        input   wire             i_ack,
        input   wire             i_wr_en,
        input   wire             i_wr_en,
 
 
 
        // Data busses
        input   wire [WIDTH-1:0] i_data,
        input   wire [WIDTH-1:0] i_data,
        output  reg [WIDTH-1:0]  o_data,
        output  reg [WIDTH-1:0]  o_data,
 
        output  reg [WIDTH-1:0]  o_data_nxt,
 
 
 
        // Flags
        output wire              o_empty,
        output wire              o_empty,
        output wire              o_full,
        output wire              o_full,
        output wire              o_empty_n,
        output wire              o_empty_n,
        output wire              o_full_n,
        output wire              o_full_n,
        output wire              o_full_n_nxt
        output wire              o_full_n_nxt
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// Xilinx ISE does not allow $CLOG2 in localparams.
// Xilinx ISE does not allow $CLOG2 in localparams.
parameter PTR_WDT = $clog2(DEPTH) + 32'd1;
parameter PTR_WDT = $clog2(DEPTH) + 32'd1;
parameter [PTR_WDT-1:0] DEFAULT = {PTR_WDT{1'd0}};
parameter [PTR_WDT-1:0] DEFAULT = {PTR_WDT{1'd0}};
 
 
//
// Variables
// Initialize pointers, empty and full as a part of the FPGA reset.
 
// All init to *ZERO*.
 
//
 
reg [PTR_WDT-1:0] rptr_ff;
reg [PTR_WDT-1:0] rptr_ff;
reg [PTR_WDT-1:0] rptr_nxt;
reg [PTR_WDT-1:0] rptr_nxt;
reg [PTR_WDT-1:0] wptr_ff;
reg [PTR_WDT-1:0] wptr_ff;
reg empty, nempty;
reg empty, nempty;
reg full, nfull;
reg full, nfull;
reg [PTR_WDT-1:0] wptr_nxt;
reg [PTR_WDT-1:0] wptr_nxt;
reg [WIDTH-1:0] mem [DEPTH-1:0]; // Block RAM.
reg [WIDTH-1:0]   mem [DEPTH-1:0];
wire [WIDTH-1:0] dt;
wire [WIDTH-1:0] dt;
reg [WIDTH-1:0] dt1;
reg [WIDTH-1:0] dt1;
 
 
reg sel_ff;
reg sel_ff;
reg [WIDTH-1:0] bram_ff; // Block RAM read register.
reg [WIDTH-1:0]   bram_ff;
reg [WIDTH-1:0] dt_ff;
reg [WIDTH-1:0] dt_ff;
 
 
 
// Assigns
assign o_empty = empty;
assign o_empty = empty;
assign o_full  = full;
assign o_full  = full;
assign o_empty_n = nempty;
assign o_empty_n = nempty;
assign o_full_n = nfull;
assign o_full_n = nfull;
 
 
assign o_full_n_nxt = i_reset ? 1 :
assign o_full_n_nxt = i_reset ? 1 :
                      !( ( wptr_nxt[PTR_WDT-2:0] == rptr_nxt[PTR_WDT-2:0] ) &&
                      !( ( wptr_nxt[PTR_WDT-2:0] == rptr_nxt[PTR_WDT-2:0] ) &&
                       ( wptr_nxt != rptr_nxt ) );
                       ( wptr_nxt != rptr_nxt ) );
 
 
 
 
// FIFO write logic.
// FIFO write logic.
always @ (posedge i_clk)
always @ (posedge i_clk)
        if ( i_wr_en && !o_full )
        if ( i_wr_en && !o_full )
                mem[wptr_ff[PTR_WDT-2:0]] <= i_data;
                mem[wptr_ff[PTR_WDT-2:0]] <= i_data;
 
 
 
// FIFO read logic
generate
generate
begin:gb1
begin:gb1
        if ( FWFT == 1 )
        if ( FWFT == 1 )
        begin:f1
        begin:f1
                // Retimed output data compared to normal FIFO.
                // Retimed output data compared to normal FIFO.
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                // Output signal steering MUX.
                // Output signal steering MUX.
                always @*
                always @*
                begin
                begin
                        o_data = sel_ff ? dt_ff : bram_ff;
                        o_data = sel_ff ? dt_ff : bram_ff;
 
                        o_data_nxt = 0; // Tied off.
                end
                end
        end
        end
        else
        else
        begin:f0
        begin:f0
                always @ (posedge i_clk)
                always @ (posedge i_clk)
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                        if ( i_ack && nempty ) // Read request and not empty.
                        if ( i_ack && nempty ) // Read request and not empty.
                        begin
                        begin
                                o_data <= mem [ rptr_ff[PTR_WDT-2:0] ];
                                o_data <= mem [ rptr_ff[PTR_WDT-2:0] ];
                        end
                        end
                end
                end
 
 
 
                if ( PROVIDE_NXT_DATA )
 
                begin: f11
 
                        always @ (*)
 
                        begin
 
                                if ( i_ack && nempty )
 
                                        o_data_nxt = mem [ rptr_ff[PTR_WDT-2:0] ];
 
                                else
 
                                        o_data_nxt = o_data;
 
                        end
 
                end
 
                else
 
                begin: f22
 
                        always @* o_data_nxt = 0;
 
                end
        end
        end
end
end
endgenerate
endgenerate
 
 
// Flip-flop update.
// Flip-flop update.
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begin
begin
        wptr_nxt = wptr_ff + (i_wr_en && !o_full);
        wptr_nxt = wptr_ff + (i_wr_en && !o_full);
        rptr_nxt = rptr_ff + (i_ack && !o_empty);
        rptr_nxt = rptr_ff + (i_ack && !o_empty);
end
end
 
 
endmodule
endmodule // zap_sync_fifo
 
 
`default_nettype wire
`default_nettype wire
 
 
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