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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_wb_adapter.v] - Diff between revs 29 and 43

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Rev 29 Rev 43
Line 53... Line 53...
output wire     [31:0]       o_wb_adr,
output wire     [31:0]       o_wb_adr,
output wire     [3:0]        o_wb_sel,
output wire     [3:0]        o_wb_sel,
output wire     [2:0]        o_wb_cti,
output wire     [2:0]        o_wb_cti,
output wire                  o_wb_we,
output wire                  o_wb_we,
input wire      [31:0]       i_wb_dat,
input wire      [31:0]       i_wb_dat,
input wire                   i_wb_ack
input wire                   i_wb_ack,
 
 
 
output reg                   o_wb_stb_nxt,
 
output reg                   o_wb_cyc_nxt,
 
output wire     [3:0]        o_wb_sel_nxt,
 
output wire     [31:0]       o_wb_dat_nxt,
 
output wire     [31:0]       o_wb_adr_nxt,
 
output wire                  o_wb_we_nxt
 
 
);
);
 
 
`include "zap_defines.vh"
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_localparams.vh"
 
 
reg  fsm_write_en;
reg  fsm_write_en;
reg  [69:0] fsm_write_data;
reg  [69:0] fsm_write_data;
wire w_eob;
wire w_eob;
wire w_full;
wire w_full;
 
wire w_eob_nxt;
 
 
assign    o_wb_cti = {w_eob, 1'd1, w_eob};
assign    o_wb_cti = {w_eob, 1'd1, w_eob};
 
 
wire w_emp;
wire w_emp;
 
 
// {SEL, DATA, ADDR, EOB, WEN} = 4 + 64 + 1 + 1 = 70 bit.
// {SEL, DATA, ADDR, EOB, WEN} = 4 + 64 + 1 + 1 = 70 bit.
zap_sync_fifo #(.WIDTH(70), .DEPTH(DEPTH), .FWFT(1'd0)) U_STORE_FIFO (
zap_sync_fifo #(.WIDTH(70), .DEPTH(DEPTH), .FWFT(1'd0), .PROVIDE_NXT_DATA(1)) U_STORE_FIFO (
.i_clk          (i_clk),
.i_clk          (i_clk),
.i_reset        (i_reset),
.i_reset        (i_reset),
.i_ack          ((i_wb_ack && o_wb_stb) || emp_ff),
.i_ack          ((i_wb_ack && o_wb_stb) || emp_ff),
.i_wr_en        (fsm_write_en),
.i_wr_en        (fsm_write_en),
.i_data         (fsm_write_data),
.i_data         (fsm_write_data),
.o_data         ({o_wb_sel, o_wb_dat, o_wb_adr, w_eob, o_wb_we}),
.o_data         ({o_wb_sel, o_wb_dat, o_wb_adr, w_eob, o_wb_we}),
 
.o_data_nxt     ({o_wb_sel_nxt, o_wb_dat_nxt, o_wb_adr_nxt, w_eob_nxt, o_wb_we_nxt}),
.o_empty        (w_emp),
.o_empty        (w_emp),
.o_full         (w_full),
.o_full         (w_full),
.o_empty_n      (),
.o_empty_n      (),
.o_full_n       (),
.o_full_n       (),
.o_full_n_nxt   ()
.o_full_n_nxt   ()
);
);
 
 
 
reg emp_nxt;
reg emp_ff;
reg emp_ff;
reg [31:0] ctr_nxt, ctr_ff;
reg [31:0] ctr_nxt, ctr_ff;
reg [31:0] dff, dnxt;
reg [31:0] dff, dnxt;
reg ack;        // ACK write channel.
reg ack;        // ACK write channel.
reg ack_ff;     // Read channel.
reg ack_ff;     // Read channel.
Line 100... Line 110...
localparam WAIT2 = 6;
localparam WAIT2 = 6;
localparam NUMBER_OF_STATES = 7;
localparam NUMBER_OF_STATES = 7;
 
 
reg [$clog2(NUMBER_OF_STATES)-1:0] state_ff, state_nxt;
reg [$clog2(NUMBER_OF_STATES)-1:0] state_ff, state_nxt;
 
 
// FIFO pipeline register.
// FIFO pipeline register and nxt state logic.
always @ (posedge i_clk)
always @ (*)
begin
begin
 
        emp_nxt      = emp_ff;
 
        o_wb_stb_nxt = o_wb_stb;
 
        o_wb_cyc_nxt = o_wb_cyc;
 
 
        if ( i_reset )
        if ( i_reset )
        begin
        begin
                emp_ff   <= 1'd1;
                emp_nxt      = 1'd1;
                o_wb_stb <= 1'd0;
                o_wb_stb_nxt = 1'd0;
                o_wb_cyc <= 1'd0;
                o_wb_cyc_nxt = 1'd0;
        end
        end
        else if ( emp_ff || (i_wb_ack && o_wb_stb) )
        else if ( emp_ff || (i_wb_ack && o_wb_stb) )
        begin
        begin
                emp_ff   <= w_emp;
                emp_nxt      = w_emp;
                o_wb_stb <= !w_emp;
                o_wb_stb_nxt = !w_emp;
                o_wb_cyc <= !w_emp;
                o_wb_cyc_nxt = !w_emp;
 
        end
        end
        end
 
 
 
always @ (posedge i_clk)
 
begin
 
        emp_ff   <= emp_nxt;
 
        o_wb_stb <= o_wb_stb_nxt;
 
        o_wb_cyc <= o_wb_cyc_nxt;
end
end
 
 
// Flip flop clocking block.
// Flip flop clocking block.
always @ (posedge i_clk)
always @ (posedge i_clk)
begin
begin
Line 184... Line 205...
                begin
                begin
                        // Write a set of reads into the FIFO.
                        // Write a set of reads into the FIFO.
                        if ( I_WB_CTI == CTI_BURST ) // Burst of 4 words. Each word is 4 byte.
                        if ( I_WB_CTI == CTI_BURST ) // Burst of 4 words. Each word is 4 byte.
                        begin
                        begin
                                state_nxt = PRPR_RD_BURST;
                                state_nxt = PRPR_RD_BURST;
                                //state_nxt = PRPR_RD_SINGLE; //PRPR_RD_BURST;
                                $display($time, " - %m :: Read burst requested. Base address = %x", I_WB_ADR);
                                $display("Read burst requested! Address base = %x", I_WB_ADR);
 
                                //$stop;
 
                        end
                        end
                        else // Single.
                        else // Single.
                        begin
                        begin
                                state_nxt = PRPR_RD_SINGLE;
                                state_nxt = PRPR_RD_SINGLE;
                        end
                        end
Line 214... Line 233...
        PRPR_RD_BURST: // Write burst read requests into the FIFO.
        PRPR_RD_BURST: // Write burst read requests into the FIFO.
        begin
        begin
                if ( O_WB_ACK )
                if ( O_WB_ACK )
                begin
                begin
                        dnxt = dff + 1'd1;
                        dnxt = dff + 1'd1;
                        $display($time, "EARLY ACK READ BURST. DATA IS %x", O_WB_DAT);
                        $display($time, " - %m :: Early response received for read burst. Data received %x", O_WB_DAT);
                        //$stop;
 
                end
                end
 
 
                if ( ctr_ff == BURST_LEN * 4 )
                if ( ctr_ff == BURST_LEN * 4 )
                begin
                begin
                        ctr_nxt = 0;
                        ctr_nxt = 0;
Line 236... Line 254...
                                                adr,
                                                adr,
                                                ctr_ff == 12 ? 1'd1 : 1'd0,
                                                ctr_ff == 12 ? 1'd1 : 1'd0,
                                                1'd0 };
                                                1'd0 };
                        ctr_nxt = ctr_ff + 4;
                        ctr_nxt = ctr_ff + 4;
 
 
                        $display($time, "READ_BURST :: Writing data SEL = %x DATA = %x ADDR = %x EOB = %x WEN = %x to the FIFO", fsm_write_data[69:66], fsm_write_data[65:34], fsm_write_data[33:2], fsm_write_data[1], fsm_write_data[0]);
                        $display($time, " - %m :: Read Burst. Writing data SEL = %x DATA = %x ADDR = %x EOB = %x WEN = %x to the FIFO",
                        //$stop;
                        fsm_write_data[69:66], fsm_write_data[65:34], fsm_write_data[33:2], fsm_write_data[1], fsm_write_data[0]);
                end
                end
        end
        end
 
 
        WRITE:
        WRITE:
        begin
        begin
Line 272... Line 290...
        WAIT2: // Wait for burst reads to complete.
        WAIT2: // Wait for burst reads to complete.
        begin
        begin
                if ( O_WB_ACK )
                if ( O_WB_ACK )
                begin
                begin
                        dnxt = dff + 1;
                        dnxt = dff + 1;
                        $display("READ BURST! ACK sent. Data provided is %x", O_WB_DAT);
                        $display($time, " - %m :: Read Burst. ACK sent. Data provided is %x", O_WB_DAT);
                        //$stop;
 
                end
                end
 
 
                if ( dff == BURST_LEN && !o_wb_stb )
                if ( dff == BURST_LEN && !o_wb_stb )
                begin
                begin
                        state_nxt = IDLE;
                        state_nxt = IDLE;

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