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[/] [zap/] [trunk/] [src/] [rtl/] [cpu/] [zap_writeback.v] - Diff between revs 43 and 51

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Rev 43 Rev 51
Line 117... Line 117...
 
 
`include "zap_defines.vh"
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
`include "zap_functions.vh"
 
 
// ----------------------------------------------
// ----------------------------------------------------------------------------
// Localparams
// Localparams
// ----------------------------------------------
// ----------------------------------------------------------------------------
 
 
`ifndef ARM_MODE
`ifndef ARM_MODE
        `define ARM_MODE (cpsr_ff[T] == 1'd0)
        `define ARM_MODE (cpsr_ff[T] == 1'd0)
`endif
`endif
 
 
Line 133... Line 133...
localparam PABT_VECTOR  = 32'h0000000C;
localparam PABT_VECTOR  = 32'h0000000C;
localparam DABT_VECTOR  = 32'h00000010;
localparam DABT_VECTOR  = 32'h00000010;
localparam IRQ_VECTOR   = 32'h00000018;
localparam IRQ_VECTOR   = 32'h00000018;
localparam FIQ_VECTOR   = 32'h0000001C;
localparam FIQ_VECTOR   = 32'h0000001C;
 
 
// ----------------------------------------------
// ----------------------------------------------------------------------------
// Variables
// Variables
// ----------------------------------------------
// ----------------------------------------------------------------------------
 
 
// assertions_start
 
        reg fiq_ack;
 
        reg irq_ack;
 
        reg und_ack;
 
        reg dabt_ack;
 
        reg iabt_ack;
 
        reg swi_ack;
 
        integer irq_addr = 0;
 
        reg temp_set = 0;
 
        reg error = 0;
 
// assertions_end
 
 
 
reg     [31:0]                  cpsr_ff, cpsr_nxt;
reg     [31:0]                  cpsr_ff, cpsr_nxt;
reg     [31:0]                  pc_ff, pc_nxt;
reg     [31:0]                  pc_ff, pc_nxt;
reg [$clog2(PHY_REGS)-1:0]      wa1, wa2;
reg [$clog2(PHY_REGS)-1:0]      wa1, wa2;
reg [31:0]                      wdata1, wdata2;
reg [31:0]                      wdata1, wdata2;
Line 162... Line 150...
assign  o_shelve        = shelve_ff; // Shelve the PC until it is needed.
assign  o_shelve        = shelve_ff; // Shelve the PC until it is needed.
assign  o_pc            = pc_ff;
assign  o_pc            = pc_ff;
assign  o_pc_nxt        = pc_nxt & 32'hfffffffe;
assign  o_pc_nxt        = pc_nxt & 32'hfffffffe;
assign  o_cpsr_nxt      = cpsr_nxt;
assign  o_cpsr_nxt      = cpsr_nxt;
 
 
// ----------------------------------------------
// ----------------------------------------------------------------------------
// Register file
// Register file
// ----------------------------------------------
// ----------------------------------------------------------------------------
 
 
zap_register_file u_zap_register_file
zap_register_file u_zap_register_file
(
(
.i_clk(i_clk),
.i_clk(i_clk),
 .i_reset        (       i_reset         ),
 .i_reset        (       i_reset         ),
Line 190... Line 178...
 .o_rd_data_b    (       o_rd_data_1     ),
 .o_rd_data_b    (       o_rd_data_1     ),
 .o_rd_data_c    (       o_rd_data_2     ),
 .o_rd_data_c    (       o_rd_data_2     ),
 .o_rd_data_d    (       o_rd_data_3     )
 .o_rd_data_d    (       o_rd_data_3     )
);
);
 
 
// ---------------------------------------------
// ----------------------------------------------------------------------------
// Combinational Logic
// Combinational Logic
// ---------------------------------------------
// ----------------------------------------------------------------------------
 
 
always @ (*)
always @ (*)
begin: blk1
begin: blk1
 
 
        integer i;
        integer i;
 
 
        shelve_nxt    = shelve_ff;
        shelve_nxt    = shelve_ff;
        pc_shelve_nxt = pc_shelve_ff;
        pc_shelve_nxt = pc_shelve_ff;
 
 
        // assertions_start
 
                fiq_ack  = 0;
 
                irq_ack  = 0;
 
                und_ack  = 0;
 
                dabt_ack = 0;
 
                iabt_ack = 0;
 
                swi_ack  = 0;
 
        // assertions_end
 
 
 
        o_hijack     = 0;
        o_hijack     = 0;
        o_hijack_op1 = 0;
        o_hijack_op1 = 0;
        o_hijack_op2 = 0;
        o_hijack_op2 = 0;
        o_hijack_cin = 0;
        o_hijack_cin = 0;
 
 
Line 289... Line 268...
                wdata1                  = `ARM_MODE ? i_pc_buf_ff : i_hijack_sum[31:0];
                wdata1                  = `ARM_MODE ? i_pc_buf_ff : i_hijack_sum[31:0];
                wa1                     = PHY_ABT_R14;
                wa1                     = PHY_ABT_R14;
                wa2                     = PHY_ABT_SPSR;
                wa2                     = PHY_ABT_SPSR;
                wdata2                  = cpsr_ff;
                wdata2                  = cpsr_ff;
                cpsr_nxt[`CPSR_MODE]    = ABT;
                cpsr_nxt[`CPSR_MODE]    = ABT;
 
 
                // assertions_start
 
                        dabt_ack = 1'd1;
 
                // assertions_end
 
 
 
        end
        end
        else if ( i_fiq )
        else if ( i_fiq )
        begin
        begin
                $display($time, " - %m :: FIQ detected.");
 
 
 
                // Returns do LR - 4 to get back to the same instruction.
                // Returns do LR - 4 to get back to the same instruction.
                pc_shelve ( FIQ_VECTOR );
                pc_shelve ( FIQ_VECTOR );
 
 
                wen                     = 1;
                wen                     = 1;
                wdata1                  = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wdata1                  = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wa1                     = PHY_FIQ_R14;
                wa1                     = PHY_FIQ_R14;
                wa2                     = PHY_FIQ_SPSR;
                wa2                     = PHY_FIQ_SPSR;
                wdata2                  = cpsr_ff;
                wdata2                  = cpsr_ff;
                cpsr_nxt[`CPSR_MODE]    = FIQ;
                cpsr_nxt[`CPSR_MODE]    = FIQ;
                cpsr_nxt[F]             = 1'd1;
                cpsr_nxt[F]             = 1'd1;
 
 
                // assertions_start
 
                        fiq_ack = 1'd1;
 
                // assertions_end
 
        end
        end
        else if ( i_irq )
        else if ( i_irq )
        begin
        begin
                $display($time, " - %m :: IRQ detected.");
 
 
 
                pc_shelve (IRQ_VECTOR);
                pc_shelve (IRQ_VECTOR);
 
 
                wen                     = 1;
                wen                     = 1;
                wdata1                  = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wdata1                  = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wa1                     = PHY_IRQ_R14;
                wa1                     = PHY_IRQ_R14;
                wa2                     = PHY_IRQ_SPSR;
                wa2                     = PHY_IRQ_SPSR;
                wdata2                  = cpsr_ff;
                wdata2                  = cpsr_ff;
                cpsr_nxt[`CPSR_MODE]    = IRQ;
                cpsr_nxt[`CPSR_MODE]    = IRQ;
                // Returns do LR - 4 to get back to the same instruction.
                // Returns do LR - 4 to get back to the same instruction.
 
 
                // assertions_start
 
                        irq_addr = wdata1;
 
                        irq_ack  = 1'd1;
 
                // assertions_end
 
        end
        end
        else if ( i_instr_abt )
        else if ( i_instr_abt )
        begin
        begin
                // Returns do LR - 4 to get back to the same instruction.
                // Returns do LR - 4 to get back to the same instruction.
                pc_shelve (PABT_VECTOR);
                pc_shelve (PABT_VECTOR);
Line 344... Line 305...
                wdata1 = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wdata1 = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wa1    = PHY_ABT_R14;
                wa1    = PHY_ABT_R14;
                wa2    = PHY_ABT_SPSR;
                wa2    = PHY_ABT_SPSR;
                wdata2 = cpsr_ff;
                wdata2 = cpsr_ff;
                cpsr_nxt[`CPSR_MODE]  = ABT;
                cpsr_nxt[`CPSR_MODE]  = ABT;
 
 
                // assertions_start
 
                        iabt_ack = 1'd1;
 
                // assertions_end
 
        end
        end
        else if ( i_swi )
        else if ( i_swi )
        begin
        begin
                // Returns do LR to return to the next instruction.
                // Returns do LR to return to the next instruction.
                pc_shelve(SWI_VECTOR);
                pc_shelve(SWI_VECTOR);
Line 360... Line 317...
                wdata1                  = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wdata1                  = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wa1                     = PHY_SVC_R14;
                wa1                     = PHY_SVC_R14;
                wa2                     = PHY_SVC_SPSR;
                wa2                     = PHY_SVC_SPSR;
                wdata2                  = cpsr_ff;
                wdata2                  = cpsr_ff;
                cpsr_nxt[`CPSR_MODE]    = SVC;
                cpsr_nxt[`CPSR_MODE]    = SVC;
 
 
                // assertions_start
 
                        swi_ack = 1'd1;
 
                // assertions_end
 
        end
        end
        else if ( i_und )
        else if ( i_und )
        begin
        begin
                // Returns do LR to return to the next instruction.
                // Returns do LR to return to the next instruction.
                pc_shelve(UND_VECTOR);
                pc_shelve(UND_VECTOR);
Line 376... Line 329...
                wdata1                  = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wdata1                  = `ARM_MODE ? i_wr_data : i_pc_buf_ff ;
                wa1                     = PHY_UND_R14;
                wa1                     = PHY_UND_R14;
                wa2                     = PHY_UND_SPSR;
                wa2                     = PHY_UND_SPSR;
                wdata2                  = cpsr_ff;
                wdata2                  = cpsr_ff;
                cpsr_nxt[`CPSR_MODE]    = UND;
                cpsr_nxt[`CPSR_MODE]    = UND;
 
 
                // assertions_start
 
                        und_ack = 1'd1;
 
                // assertions_end
 
        end
        end
        else if ( i_copro_reg_en )
        else if ( i_copro_reg_en )
        begin
        begin
               // Write to register (Coprocessor command).
               // Write to register (Coprocessor command).
               wen      = 1;
               wen      = 1;
Line 407... Line 356...
                wdata2 = i_wr_data_1;
                wdata2 = i_wr_data_1;
 
 
                // Load to PC will trigger from writeback.
                // Load to PC will trigger from writeback.
                if ( i_mem_load_ff && i_wr_index_1 == ARCH_PC)
                if ( i_mem_load_ff && i_wr_index_1 == ARCH_PC)
                begin
                begin
                        $display($time, " - %m :: Detected load to PC. Trigger a writeback.");
 
 
 
                        pc_shelve (i_wr_data_1);
                        pc_shelve (i_wr_data_1);
                        o_clear_from_writeback  = 1'd1;
                        o_clear_from_writeback  = 1'd1;
                end
                end
        end
        end
 
 
        // Ensure lower 2 bits of PC are always tied to VSS.
        // Ensure lower 2 bits of PC are always tied to VSS.
        pc_nxt = pc_nxt & 32'hffff_fffe;
        pc_nxt = pc_nxt & 32'hffff_fffe;
end
end
 
 
// ----------------------------------------------
// ----------------------------------------------------------------------------
// Sequential Logic
// Sequential Logic
// ----------------------------------------------
// ----------------------------------------------------------------------------
 
 
always @ ( posedge i_clk )
always @ ( posedge i_clk )
begin
begin
        if ( i_reset )
        if ( i_reset )
        begin
        begin
Line 446... Line 393...
                o_decompile               <= i_decompile;
                o_decompile               <= i_decompile;
                o_copro_reg_rd_data_ff    <= o_rd_data_0;
                o_copro_reg_rd_data_ff    <= o_rd_data_0;
        end
        end
end
end
 
 
// ----------------------------------------------
// ----------------------------------------------------------------------------
// Tasks
// Tasks
// ----------------------------------------------
// ----------------------------------------------------------------------------
 
 
task pc_shelve (input [31:0] new_pc);
task pc_shelve (input [31:0] new_pc);
begin
begin
        if (!i_code_stall )
        if (!i_code_stall )
        begin
        begin
Line 466... Line 413...
                pc_nxt = pc_ff;
                pc_nxt = pc_ff;
        end
        end
end
end
endtask
endtask
 
 
// assertions_start 
 
 
 
        always @ (*)
        always @ (*)
        if ( cpsr_nxt[`CPSR_MODE] != USR && cpsr_ff[`CPSR_MODE] == USR )
        if ( cpsr_nxt[`CPSR_MODE] != USR && cpsr_ff[`CPSR_MODE] == USR )
        begin
        begin
                if (
                if (
                        i_data_abt      ||
                        i_data_abt      ||
Line 489... Line 434...
                        $display($time, "Error : %m CPU is changing out of USR mode without an exception...");
                        $display($time, "Error : %m CPU is changing out of USR mode without an exception...");
                        $stop;
                        $stop;
                end
                end
        end
        end
 
 
// assertions_end
 
 
 
endmodule // zap_register_file.v
endmodule // zap_register_file.v
 
 
`default_nettype wire
`default_nettype wire
 
 
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// ----------------------------------------------------------------------------
 
// END OF FILE
 
// ----------------------------------------------------------------------------
 
 
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