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[/] [zap/] [trunk/] [src/] [scripts/] [Config.cfg_template] - Diff between revs 41 and 43

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Rev 41 Rev 43
Line 38... Line 38...
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        STORE_BUFFER_DEPTH          => 8,       # Store buffer depth.
        STORE_BUFFER_DEPTH          => 8,       # Store buffer depth.
        SYNTHESIS                   => 1,       # Make this to 1 to simulate compile from a synthesis perspective.
        SYNTHESIS                   => 1,       # Make this to 1 to simulate compile from a synthesis perspective.
 
 
        # Testbench configuration.
        # Testbench configuration.
        UART_TX_TERMINAL            => 1,       # 1 Enables UART TX terminal. 0 disables it.
        WAVES                       => 0,       # 1 Enables wave logging.
 
        UART0_TX_TERMINAL           => 1,       # 1 Enables UART TX terminal 0. 0 disables it.
 
        UART1_TX_TERMINAL           => 1,       # 1 Enables UART TX terminal 1. 0 disables it.
 
        UART0_RX_TERMINAL           => 1,       # RX terminal 0. Characters typed go to UART RX.
 
        UART1_RX_TERMINAL           => 1,       # RX terminal 1. Characters typed go to UART RX.
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        MAX_CLOCK_CYCLES            => 100000,  # Clock cycles to run the simulation for.
        MAX_CLOCK_CYCLES            => 100000,  # Clock cycles to run the simulation for.
        ALLOW_STALLS                => 1,       # Make this 1 to allow external RAM to signal a stall.
 
        DEFINE_TLB_DEBUG            => 0,       # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
 
        REG_CHECK                   => {"r1" => "32'h4",
        REG_CHECK                   => {"r1" => "32'h4",
                                        "r2" => "32'd3"},      # Make this an anonymous has with entries like "r10" => "32'h0" etc.
                                        "r2" => "32'd3"},      # Make this an anonymous has with entries like "r10" => "32'h0" etc.
        FINAL_CHECK                 => {"32'h100" => "32'd4",
        FINAL_CHECK                 => {"32'h100" => "32'd4",
                                        "32'h66" => "32'h4"}       # Make this an anonymous hash with entries like verilog_address => verilog_value etc.
                                        "32'h66" => "32'h4"}       # Make this an anonymous hash with entries like verilog_address => verilog_value etc.
);
);

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