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/*
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* Copyright (c) 2008 Zeus Gomez Marmolejo <zeus@opencores.org>
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*
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* This file is part of the Zet processor. This processor is free
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* hardware; you can redistribute it and/or modify it under the terms of
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* the GNU General Public License as published by the Free Software
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* Foundation; either version 3, or (at your option) any later version.
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*
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* Zet is distrubuted in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Zet; see the file COPYING. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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`timescale 1ns/10ps
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module alu (
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input [31:0] x,
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input [15:0] y,
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output [31:0] out,
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input [ 2:0] t,
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input [ 2:0] func,
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input [15:0] iflags,
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output [ 8:0] oflags,
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input word_op,
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input [15:0] seg,
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input [15:0] off,
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input clk,
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output div_exc
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);
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// Net declarations
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wire [15:0] add, log, shi, rot;
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wire [8:0] othflags;
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wire [19:0] oth;
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wire [31:0] cnv, mul;
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wire af_add, af_cnv;
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wire cf_cnv, cf_add, cf_mul, cf_log, cf_shi, cf_rot;
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wire of_cnv, of_add, of_mul, of_log, of_shi, of_rot;
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wire ofi, sfi, zfi, afi, pfi, cfi;
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wire ofo, sfo, zfo, afo, pfo, cfo;
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wire flags_unchanged;
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wire dexc;
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// Module instances
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addsub add1 (x[15:0], y, add, func, word_op, cfi, cf_add, af_add, of_add);
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conv cnv2 (
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.x (x[15:0]),
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.func (func),
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.out (cnv),
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.iflags ({afi, cfi}),
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.oflags ({af_cnv, of_cnv, cf_cnv})
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);
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muldiv mul3 (
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.x (x),
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.y (y),
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.o (mul),
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.f (func),
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.word_op (word_op),
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.cfo (cf_mul),
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.ofo (of_mul),
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.clk (clk),
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.exc (dexc)
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);
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bitlog log4 (x[15:0], y, log, func, cf_log, of_log);
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shifts shi5 (x[15:0], y[4:0], shi, func[1:0], word_op, cfi, ofi, cf_shi, of_shi);
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rotate rot6 (x[15:0], y[4:0], func[1:0], cfi, word_op, rot, cf_rot, ofi, of_rot);
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othop oth7 (x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
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mux8_16 m0(t, {8'd0, y[7:0]}, add, cnv[15:0],
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mul[15:0], log, shi, rot, oth[15:0], out[15:0]);
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mux8_16 m1(t, 16'd0, 16'd0, cnv[31:16], mul[31:16],
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16'd0, 16'd0, 16'd0, {12'b0,oth[19:16]}, out[31:16]);
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mux8_1 a1(t, 1'b0, cf_add, cf_cnv, cf_mul, cf_log, cf_shi, cf_rot, 1'b0, cfo);
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mux8_1 a2(t, 1'b0, af_add, af_cnv, 1'b0, 1'b0, 1'b0, afi, 1'b0, afo);
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mux8_1 a3(t, 1'b0, of_add, of_cnv, of_mul, of_log, of_shi, of_rot, 1'b0, ofo);
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// Flags
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assign pfo = flags_unchanged ? pfi : ^~ out[7:0];
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assign zfo = flags_unchanged ? zfi
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: ((word_op && (t!=3'd2)) ? ~|out[15:0] : ~|out[7:0]);
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assign sfo = flags_unchanged ? sfi
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: ((word_op && (t!=3'd2)) ? out[15] : out[7]);
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assign oflags = (t == 3'd7) ? othflags
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: { ofo, iflags[10:8], sfo, zfo, afo, pfo, cfo };
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assign ofi = iflags[11];
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assign sfi = iflags[7];
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assign zfi = iflags[6];
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assign afi = iflags[4];
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assign pfi = iflags[2];
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assign cfi = iflags[0];
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assign flags_unchanged = (t == 3'd4 && func == 3'd2
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|| t == 3'd5 && y[4:0] == 5'h0
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|| t == 3'd6);
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assign div_exc = func[1] && (t==3'd3) && dexc;
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endmodule
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module addsub (
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input [15:0] x,
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input [15:0] y,
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output [15:0] out,
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input [ 2:0] f,
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input word_op,
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input cfi,
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output cfo,
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output afo,
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output ofo
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);
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// Net declarations
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wire [15:0] op2;
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wire ci;
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wire cfoadd;
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wire xs, ys, os;
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// Module instances
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fulladd16 fa0 ( // We instantiate only one adder
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.x (x), // to have less hardware
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.y (op2),
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.ci (ci),
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.co (cfoadd),
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.z (out),
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.s (f[2])
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);
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// Assignments
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assign op2 = f[2] ? ~y
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: ((f[1:0]==2'b11) ? { 8'b0, y[7:0] } : y);
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assign ci = f[2] & f[1] | f[2] & ~f[0] & ~cfi
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| f[2] & f[0] | (f==3'b0) & cfi;
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assign afo = f[1] ? (f[2] ? &out[3:0] : ~|out[3:0] )
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: (x[4] ^ y[4] ^ out[4]);
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assign cfo = f[1] ? cfi /* inc, dec */
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: (word_op ? cfoadd : (x[8]^y[8]^out[8]));
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assign xs = word_op ? x[15] : x[7];
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assign ys = word_op ? y[15] : y[7];
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assign os = word_op ? out[15] : out[7];
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assign ofo = f[2] ? (~xs & ys & os | xs & ~ys & ~os)
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: (~xs & ~ys & os | xs & ys & ~os);
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endmodule
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module conv (
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input [15:0] x,
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input [ 2:0] func,
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output [31:0] out,
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input [ 1:0] iflags, // afi, cfi
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output [ 2:0] oflags // afo, ofo, cfo
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);
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// Net declarations
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wire afi, cfi;
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wire ofo, afo, cfo;
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wire [15:0] aaa, aas;
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wire [ 7:0] daa, tmpdaa, das, tmpdas;
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wire [15:0] cbw, cwd;
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wire acond, dcond;
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wire tmpcf;
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// Module instances
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mux8_16 m0(func, cbw, aaa, aas, 16'd0,
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cwd, {x[15:8], daa}, {x[15:8], das}, 16'd0, out[15:0]);
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// Assignments
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assign aaa = (acond ? (x + 16'h0106) : x) & 16'hff0f;
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assign aas = (acond ? (x - 16'h0106) : x) & 16'hff0f;
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assign tmpdaa = acond ? (x[7:0] + 8'h06) : x[7:0];
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assign daa = dcond ? (tmpdaa + 8'h60) : tmpdaa;
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assign tmpdas = acond ? (x[7:0] - 8'h06) : x[7:0];
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assign das = dcond ? (tmpdas - 8'h60) : tmpdas;
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assign cbw = { { 8{x[ 7]}}, x[7:0] };
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assign { out[31:16], cwd } = { {16{x[15]}}, x };
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assign acond = ((x[7:0] & 8'h0f) > 8'h09) | afi;
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assign dcond = (x[7:0] > 8'h99) | cfi;
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assign afi = iflags[1];
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assign cfi = iflags[0];
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assign afo = acond;
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assign ofo = 1'b0;
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assign tmpcf = (x[7:0] < 8'h06) | cfi;
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assign cfo = func[2] ? (dcond ? 1'b1 : (acond & tmpcf))
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: acond;
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assign oflags = { afo, ofo, cfo };
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endmodule
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module muldiv (
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input [31:0] x, // 16 MSb for division
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input [15:0] y,
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output [31:0] o,
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input [ 2:0] f,
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input word_op,
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output cfo,
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output ofo,
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input clk,
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output exc
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);
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// Net declarations
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wire as, bs, cfs, cfu;
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wire [16:0] a, b;
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wire [33:0] p;
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wire div0, over, ovf, mint;
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wire [33:0] zi;
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wire [16:0] di;
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wire [17:0] q;
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wire [17:0] s;
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// Module instantiations
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mult signmul17 (
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.clk (clk),
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.a (a),
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.b (b),
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.p (p)
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);
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div_su #(34) dut (
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.clk (clk),
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.ena (1'b1),
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.z (zi),
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.d (di),
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.q (q),
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.s (s),
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.ovf (ovf),
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.div0 (div0)
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);
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// Sign ext. for imul
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assign as = f[0] & (word_op ? x[15] : x[7]);
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assign bs = f[0] & (word_op ? y[15] : y[7]);
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assign a = word_op ? { as, x[15:0] }
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: { {9{as}}, x[7:0] };
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assign b = word_op ? { bs, y } : { {9{bs}}, y[7:0] };
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assign zi = f[2] ? { 26'h0, x[7:0] }
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: (word_op ? (f[0] ? { {2{x[31]}}, x }
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: { 2'b0, x })
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: (f[0] ? { {18{x[15]}}, x[15:0] }
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: { 18'b0, x[15:0] }));
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assign di = word_op ? (f[0] ? { y[15], y } : { 1'b0, y })
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: (f[0] ? { {9{y[7]}}, y[7:0] }
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: { 9'h000, y[7:0] });
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assign o = f[2] ? { 16'h0, q[7:0], s[7:0] }
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: (f[1] ? ( word_op ? {s[15:0], q[15:0]}
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: {16'h0, s[7:0], q[7:0]})
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: p[31:0]);
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assign ofo = f[1] ? 1'b0 : cfo;
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assign cfo = f[1] ? 1'b0 : !(f[0] ? cfs : cfu);
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assign cfu = word_op ? (o[31:16] == 16'h0)
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: (o[15:8] == 8'h0);
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assign cfs = word_op ? (o[31:16] == {16{o[15]}})
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: (o[15:8] == {8{o[7]}});
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// Exceptions
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assign over = f[2] ? 1'b0
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: (word_op ? (f[0] ? (q[17:16]!={2{q[15]}})
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: (q[17:16]!=2'b0) )
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: (f[0] ? (q[17:8]!={10{q[7]}})
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: (q[17:8]!=10'h000)));
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assign mint = f[0] & (word_op ? (x==32'h80000000)
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: (x==16'h8000));
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assign exc = div0 | (!f[2] & ovf) | over | mint;
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endmodule
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module bitlog(x, y, out, func, cfo, ofo);
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// IO ports
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input [15:0] x, y;
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input [2:0] func;
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output [15:0] out;
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output cfo, ofo;
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// Net declarations
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wire [15:0] and_n, or_n, not_n, xor_n;
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// Module instantiations
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mux8_16 m0(func, and_n, or_n, not_n, xor_n, 16'd0, 16'd0, 16'd0, 16'd0, out);
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// Assignments
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assign and_n = x & y;
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assign or_n = x | y;
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assign not_n = ~x;
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assign xor_n = x ^ y;
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assign cfo = 1'b0;
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assign ofo = 1'b0;
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endmodule
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//
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// This module implements the instructions shl/sal, sar, shr
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//
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module shifts(x, y, out, func, word_op, cfi, ofi, cfo, ofo);
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// IO ports
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input [15:0] x;
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input [ 4:0] y;
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input [1:0] func;
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input word_op;
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output [15:0] out;
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output cfo, ofo;
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input cfi, ofi;
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// Net declarations
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wire [15:0] sal, sar, shr, sal16, sar16, shr16;
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wire [7:0] sal8, sar8, shr8;
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wire ofo_shl, ofo_sar, ofo_shr;
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wire cfo_sal8, cfo_sal16, cfo_sar8, cfo_sar16, cfo_shr8, cfo_shr16;
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wire cfo16, cfo8;
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wire unchanged;
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// Module instantiations
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mux4_16 m0(func, sal, sar, shr, 16'd0, out);
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// Assignments
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assign { cfo_sal16, sal16 } = x << y;
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assign { sar16, cfo_sar16 } = (y > 5'd16) ? 17'h1ffff
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: (({x,1'b0} >> y) | (x[15] ? (17'h1ffff << (17 - y))
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: 17'h0));
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assign { shr16, cfo_shr16 } = ({x,1'b0} >> y);
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assign { cfo_sal8, sal8 } = x[7:0] << y;
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assign { sar8, cfo_sar8 } = (y > 5'd8) ? 9'h1ff
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: (({x[7:0],1'b0} >> y) | (x[7] ? (9'h1ff << (9 - y))
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: 9'h0));
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assign { shr8, cfo_shr8 } = ({x[7:0],1'b0} >> y);
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assign sal = word_op ? sal16 : { 8'd0, sal8 };
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assign shr = word_op ? shr16 : { 8'd0, shr8 };
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assign sar = word_op ? sar16 : { {8{sar8[7]}}, sar8 };
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assign ofo = unchanged ? ofi
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: (func[1] ? ofo_shr : (func[0] ? ofo_sar : ofo_shl));
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assign cfo16 = func[1] ? cfo_shr16
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: (func[0] ? cfo_sar16 : cfo_sal16);
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assign cfo8 = func[1] ? cfo_shr8
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: (func[0] ? cfo_sar8 : cfo_sal8);
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assign cfo = unchanged ? cfi : (word_op ? cfo16 : cfo8);
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assign ofo_shl = word_op ? (out[15] != cfo) : (out[7] != cfo);
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assign ofo_sar = 1'b0;
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assign ofo_shr = word_op ? x[15] : x[7];
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assign unchanged = word_op ? (y==5'b0) : (y[3:0]==4'b0);
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endmodule
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module othop (x, y, seg, off, iflags, func, word_op, out, oflags);
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// IO ports
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input [15:0] x, y, off, seg, iflags;
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input [2:0] func;
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input word_op;
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output [19:0] out;
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output [8:0] oflags;
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// Net declarations
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wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
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wire [19:0] dcmp, dcmp2;
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wire dfi;
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// Module instantiations
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mux8_16 m0(func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf,
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intf, strf, out[15:0]);
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assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];
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// Assignments
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assign dcmp = (seg << 4) + deff;
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assign dcmp2 = (seg << 4) + deff2;
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assign deff = x + y + off;
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assign deff2 = x + y + off + 16'd2;
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assign outf = y;
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assign clcm = y[2] ? (y[1] ? /* -1: clc */ {iflags[15:1], 1'b0}
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: /* 4: cld */ {iflags[15:11], 1'b0, iflags[9:0]})
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: (y[1] ? /* 2: cli */ {iflags[15:10], 1'b0, iflags[8:0]}
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: /* 0: cmc */ {iflags[15:1], ~iflags[0]});
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assign setf = y[2] ? (y[1] ? /* -1: stc */ {iflags[15:1], 1'b1}
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: /* 4: std */ {iflags[15:11], 1'b1, iflags[9:0]})
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: (y[1] ? /* 2: sti */ {iflags[15:10], 1'b1, iflags[8:0]}
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: /* 0: outf */ iflags);
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assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
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assign dfi = iflags[10];
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assign strf = dfi ? (x - y) : (x + y);
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assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
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: { iflags[11:8], out[7:6], out[4], out[2], out[0] };
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endmodule
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No newline at end of file
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