/*
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/*
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* PS2 Wishbone 8042 compatible keyboard controller
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* PS2 Wishbone 8042 compatible keyboard controller
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*
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*
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* Copyright (c) 2009 Zeus Gomez Marmolejo <zeus@opencores.org>
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* Copyright (c) 2009 Zeus Gomez Marmolejo <zeus@opencores.org>
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* adapted from the opencores keyboard controller from John Clayton
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* adapted from the opencores keyboard controller from John Clayton
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*
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*
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* This file is part of the Zet processor. This processor is free
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* This file is part of the Zet processor. This processor is free
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* hardware; you can redistribute it and/or modify it under the terms of
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* hardware; you can redistribute it and/or modify it under the terms of
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* the GNU General Public License as published by the Free Software
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* the GNU General Public License as published by the Free Software
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* Foundation; either version 3, or (at your option) any later version.
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* Foundation; either version 3, or (at your option) any later version.
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*
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*
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* Zet is distrubuted in the hope that it will be useful, but WITHOUT
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* Zet is distrubuted in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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* License for more details.
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*
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*
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* You should have received a copy of the GNU General Public License
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* You should have received a copy of the GNU General Public License
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* along with Zet; see the file COPYING. If not, see
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* along with Zet; see the file COPYING. If not, see
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* <http://www.gnu.org/licenses/>.
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* <http://www.gnu.org/licenses/>.
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*/
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*/
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`include "defines.v"
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`timescale 1ns/100ps
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`timescale 1ns/100ps
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`define TOTAL_BITS 11
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`define TOTAL_BITS 11
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`define RELEASE_CODE 16'hF0
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`define RELEASE_CODE 16'hF0
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`define LEFT_SHIFT 16'h12
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`define LEFT_SHIFT 16'h12
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`define RIGHT_SHIFT 16'h59
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`define RIGHT_SHIFT 16'h59
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module ps2_keyb (
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module ps2_keyb (
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`ifdef DEBUG
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output rx_output_strobe,
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output released,
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output rx_shifting_done,
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`endif
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// Wishbone slave interface
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// Wishbone slave interface
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input wb_clk_i,
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input wb_clk_i,
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input wb_rst_i,
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input wb_rst_i,
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output reg [7:0] wb_dat_o, // scancode
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output reg [7:0] wb_dat_o, // scancode
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output reg wb_tgc_o, // intr
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output reg wb_tgc_o, // intr
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input wb_tgc_i, // inta
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// PS2 PAD signals
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// PS2 PAD signals
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inout ps2_clk_,
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inout ps2_clk_,
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inout ps2_data_
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inout ps2_data_
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);
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);
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// Parameter declarations
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// Parameter declarations
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// The timer value can be up to (2^bits) inclusive.
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// The timer value can be up to (2^bits) inclusive.
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parameter TIMER_60USEC_VALUE_PP = 1920; // Number of sys_clks for 60usec.
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parameter TIMER_60USEC_VALUE_PP = 1920; // Number of sys_clks for 60usec.
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parameter TIMER_60USEC_BITS_PP = 11; // Number of bits needed for timer
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parameter TIMER_60USEC_BITS_PP = 11; // Number of bits needed for timer
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parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce
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parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce
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parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer
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parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer
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parameter TRAP_SHIFT_KEYS_PP = 0; // Default: No shift key trap.
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parameter TRAP_SHIFT_KEYS_PP = 0; // Default: No shift key trap.
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// State encodings, provided as parameters
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// State encodings, provided as parameters
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// for flexibility to the one instantiating the module.
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// for flexibility to the one instantiating the module.
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// In general, the default values need not be changed.
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// In general, the default values need not be changed.
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// State "m1_rx_clk_l" has been chosen on purpose. Since the input
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// State "m1_rx_clk_l" has been chosen on purpose. Since the input
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// synchronizing flip-flops initially contain zero, it takes one clk
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// synchronizing flip-flops initially contain zero, it takes one clk
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// for them to update to reflect the actual (idle = high) status of
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// for them to update to reflect the actual (idle = high) status of
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// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
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// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
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// allows the state machine to transition to m1_rx_clk_h when the true
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// allows the state machine to transition to m1_rx_clk_h when the true
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// values of the input signals become present at the outputs of the
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// values of the input signals become present at the outputs of the
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// synchronizing flip-flops. This initial transition is harmless, and it
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// synchronizing flip-flops. This initial transition is harmless, and it
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// eliminates the need for a "reset" pulse before the interface can operate.
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// eliminates the need for a "reset" pulse before the interface can operate.
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parameter m1_rx_clk_h = 1;
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parameter m1_rx_clk_h = 1;
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parameter m1_rx_clk_l = 0;
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parameter m1_rx_clk_l = 0;
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parameter m1_rx_falling_edge_marker = 13;
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parameter m1_rx_falling_edge_marker = 13;
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parameter m1_rx_rising_edge_marker = 14;
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parameter m1_rx_rising_edge_marker = 14;
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parameter m1_tx_force_clk_l = 3;
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parameter m1_tx_force_clk_l = 3;
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parameter m1_tx_first_wait_clk_h = 10;
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parameter m1_tx_first_wait_clk_h = 10;
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parameter m1_tx_first_wait_clk_l = 11;
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parameter m1_tx_first_wait_clk_l = 11;
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parameter m1_tx_reset_timer = 12;
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parameter m1_tx_reset_timer = 12;
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parameter m1_tx_wait_clk_h = 2;
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parameter m1_tx_wait_clk_h = 2;
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parameter m1_tx_clk_h = 4;
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parameter m1_tx_clk_h = 4;
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parameter m1_tx_clk_l = 5;
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parameter m1_tx_clk_l = 5;
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parameter m1_tx_wait_keyboard_ack = 6;
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parameter m1_tx_wait_keyboard_ack = 6;
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parameter m1_tx_done_recovery = 7;
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parameter m1_tx_done_recovery = 7;
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parameter m1_tx_error_no_keyboard_ack = 8;
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parameter m1_tx_error_no_keyboard_ack = 8;
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parameter m1_tx_rising_edge_marker = 9;
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parameter m1_tx_rising_edge_marker = 9;
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// Nets and registers
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// Nets and registers
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wire rx_output_event;
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wire rx_output_event;
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wire rx_output_strobe;
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wire rx_shifting_done;
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wire tx_shifting_done;
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wire tx_shifting_done;
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wire timer_60usec_done;
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wire timer_60usec_done;
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wire timer_5usec_done;
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wire timer_5usec_done;
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`ifndef DEBUG
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wire rx_output_strobe;
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wire rx_shifting_done;
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wire released;
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wire released;
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`endif
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wire [6:0] xt_code;
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wire [6:0] xt_code;
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reg [3:0] bit_count;
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reg [3:0] bit_count;
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reg [3:0] m1_state;
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reg [3:0] m1_state;
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reg [3:0] m1_next_state;
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reg [3:0] m1_next_state;
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reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_clk_s; // Synchronous version of this input
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reg ps2_clk_s; // Synchronous version of this input
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reg ps2_data_s; // Synchronous version of this input
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reg ps2_data_s; // Synchronous version of this input
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reg enable_timer_60usec;
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reg enable_timer_60usec;
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reg enable_timer_5usec;
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reg enable_timer_5usec;
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reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
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reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
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reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
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reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
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reg [`TOTAL_BITS-1:0] q;
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reg [`TOTAL_BITS-1:0] q;
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reg hold_released; // Holds prior value, cleared at rx_output_strobe
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reg hold_released; // Holds prior value, cleared at rx_output_strobe
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// Module instantiation
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// Module instantiation
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translate_8042 tr0 (
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translate_8042 tr0 (
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.at_code (q[7:1]),
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.at_code (q[7:1]),
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.xt_code (xt_code)
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.xt_code (xt_code)
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);
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);
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// Continuous assignments
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// Continuous assignments
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// This signal is high for one clock at the end of the timer count.
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// This signal is high for one clock at the end of the timer count.
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assign rx_shifting_done = (bit_count == `TOTAL_BITS);
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assign rx_shifting_done = (bit_count == `TOTAL_BITS);
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assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);
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assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);
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assign rx_output_event = (rx_shifting_done
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assign rx_output_event = (rx_shifting_done
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&& ~released
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&& ~released
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);
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);
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assign rx_output_strobe = (rx_shifting_done
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assign rx_output_strobe = (rx_shifting_done
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&& ~released
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&& ~released
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&& ( (TRAP_SHIFT_KEYS_PP == 0)
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&& ( (TRAP_SHIFT_KEYS_PP == 0)
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|| ( (q[8:1] != `RIGHT_SHIFT)
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|| ( (q[8:1] != `RIGHT_SHIFT)
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&&(q[8:1] != `LEFT_SHIFT)
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&&(q[8:1] != `LEFT_SHIFT)
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)
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)
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)
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)
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);
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);
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assign ps2_clk_ = ps2_clk_hi_z ? 1'bZ : 1'b0;
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assign ps2_clk_ = ps2_clk_hi_z ? 1'bZ : 1'b0;
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assign ps2_data_ = ps2_data_hi_z ? 1'bZ : 1'b0;
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assign ps2_data_ = ps2_data_hi_z ? 1'bZ : 1'b0;
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assign timer_60usec_done =
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assign timer_60usec_done =
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(timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));
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(timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));
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assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);
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assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);
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// Create the signals which indicate special scan codes received.
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// Create the signals which indicate special scan codes received.
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// These are the "unlatched versions."
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// These are the "unlatched versions."
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//assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;
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//assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;
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assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;
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assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;
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// Behaviour
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// Behaviour
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// intr
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// wb_tgc_o
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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wb_tgc_o <= wb_rst_i ? 1'b0
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wb_tgc_o <= wb_rst_i ? 1'b0 : rx_output_strobe;
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: ((rx_output_strobe & !wb_tgc_i) ? 1'b1
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: (wb_tgc_o ? !wb_tgc_i : 1'b0));
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// This is the shift register
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// This is the shift register
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (wb_rst_i) q <= 0;
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if (wb_rst_i) q <= 0;
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// else if (((m1_state == m1_rx_clk_h) && ~ps2_clk_s)
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// else if (((m1_state == m1_rx_clk_h) && ~ps2_clk_s)
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else if ( (m1_state == m1_rx_falling_edge_marker)
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else if ( (m1_state == m1_rx_falling_edge_marker)
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||(m1_state == m1_tx_rising_edge_marker) )
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||(m1_state == m1_tx_rising_edge_marker) )
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q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
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q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
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// This is the 60usec timer counter
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// This is the 60usec timer counter
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (~enable_timer_60usec) timer_60usec_count <= 0;
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if (~enable_timer_60usec) timer_60usec_count <= 0;
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else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
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else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
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// This is the 5usec timer counter
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// This is the 5usec timer counter
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (~enable_timer_5usec) timer_5usec_count <= 0;
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if (~enable_timer_5usec) timer_5usec_count <= 0;
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else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
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else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
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// Input "synchronizing" logic -- synchronizes the inputs to the state
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// Input "synchronizing" logic -- synchronizes the inputs to the state
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// machine clock, thus avoiding errors related to
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// machine clock, thus avoiding errors related to
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// spurious state machine transitions.
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// spurious state machine transitions.
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//
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//
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// Since the initial state of registers is zero, and the idle state
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// Since the initial state of registers is zero, and the idle state
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// of the ps2_clk and ps2_data lines is "1" (due to pullups), the
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// of the ps2_clk and ps2_data lines is "1" (due to pullups), the
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// "sense" of the ps2_clk_s signal is inverted from the true signal.
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// "sense" of the ps2_clk_s signal is inverted from the true signal.
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// This allows the state machine to "come up" in the correct
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// This allows the state machine to "come up" in the correct
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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begin
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begin
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ps2_clk_s <= ps2_clk_;
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ps2_clk_s <= ps2_clk_;
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ps2_data_s <= ps2_data_;
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ps2_data_s <= ps2_data_;
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end
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end
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// State transition logic
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// State transition logic
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always @(m1_state
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always @(m1_state
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or q
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or q
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or tx_shifting_done
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or tx_shifting_done
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or ps2_clk_s
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or ps2_clk_s
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or ps2_data_s
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or ps2_data_s
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or timer_60usec_done
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or timer_60usec_done
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or timer_5usec_done
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or timer_5usec_done
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)
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)
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begin : m1_state_logic
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begin : m1_state_logic
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// Output signals default to this value,
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// Output signals default to this value,
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// unless changed in a state condition.
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// unless changed in a state condition.
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ps2_clk_hi_z <= 1;
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ps2_clk_hi_z <= 1;
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ps2_data_hi_z <= 1;
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ps2_data_hi_z <= 1;
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enable_timer_60usec <= 0;
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enable_timer_60usec <= 0;
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enable_timer_5usec <= 0;
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enable_timer_5usec <= 0;
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case (m1_state)
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case (m1_state)
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m1_rx_clk_h :
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m1_rx_clk_h :
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begin
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begin
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enable_timer_60usec <= 1;
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enable_timer_60usec <= 1;
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if (~ps2_clk_s)
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if (~ps2_clk_s)
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m1_next_state <= m1_rx_falling_edge_marker;
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m1_next_state <= m1_rx_falling_edge_marker;
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else m1_next_state <= m1_rx_clk_h;
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else m1_next_state <= m1_rx_clk_h;
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end
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end
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m1_rx_falling_edge_marker :
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m1_rx_falling_edge_marker :
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begin
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begin
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enable_timer_60usec <= 0;
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enable_timer_60usec <= 0;
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m1_next_state <= m1_rx_clk_l;
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m1_next_state <= m1_rx_clk_l;
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end
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end
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m1_rx_rising_edge_marker :
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m1_rx_rising_edge_marker :
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begin
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begin
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enable_timer_60usec <= 0;
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enable_timer_60usec <= 0;
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m1_next_state <= m1_rx_clk_h;
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m1_next_state <= m1_rx_clk_h;
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end
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end
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m1_rx_clk_l :
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m1_rx_clk_l :
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begin
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begin
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enable_timer_60usec <= 1;
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enable_timer_60usec <= 1;
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if (ps2_clk_s)
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if (ps2_clk_s)
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m1_next_state <= m1_rx_rising_edge_marker;
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m1_next_state <= m1_rx_rising_edge_marker;
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else m1_next_state <= m1_rx_clk_l;
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else m1_next_state <= m1_rx_clk_l;
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end
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end
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m1_tx_reset_timer :
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m1_tx_reset_timer :
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begin
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begin
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enable_timer_60usec <= 0;
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enable_timer_60usec <= 0;
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m1_next_state <= m1_tx_force_clk_l;
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m1_next_state <= m1_tx_force_clk_l;
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end
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end
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m1_tx_force_clk_l :
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m1_tx_force_clk_l :
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begin
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begin
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enable_timer_60usec <= 1;
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enable_timer_60usec <= 1;
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ps2_clk_hi_z <= 0; // Force the ps2_clk line low.
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ps2_clk_hi_z <= 0; // Force the ps2_clk line low.
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if (timer_60usec_done)
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if (timer_60usec_done)
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m1_next_state <= m1_tx_first_wait_clk_h;
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m1_next_state <= m1_tx_first_wait_clk_h;
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else m1_next_state <= m1_tx_force_clk_l;
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else m1_next_state <= m1_tx_force_clk_l;
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end
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end
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m1_tx_first_wait_clk_h :
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m1_tx_first_wait_clk_h :
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begin
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begin
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enable_timer_5usec <= 1;
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enable_timer_5usec <= 1;
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ps2_data_hi_z <= 0; // Start bit.
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ps2_data_hi_z <= 0; // Start bit.
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if (~ps2_clk_s && timer_5usec_done)
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if (~ps2_clk_s && timer_5usec_done)
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m1_next_state <= m1_tx_clk_l;
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m1_next_state <= m1_tx_clk_l;
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else
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else
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m1_next_state <= m1_tx_first_wait_clk_h;
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m1_next_state <= m1_tx_first_wait_clk_h;
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end
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end
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// This state must be included because the device might possibly
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// This state must be included because the device might possibly
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// delay for up to 10 milliseconds before beginning its clock pulses.
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// delay for up to 10 milliseconds before beginning its clock pulses.
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// During that waiting time, we cannot drive the data (q[0]) because it
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// During that waiting time, we cannot drive the data (q[0]) because it
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// is possibly 1, which would cause the keyboard to abort its receive
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// is possibly 1, which would cause the keyboard to abort its receive
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// and the expected clocks would then never be generated.
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// and the expected clocks would then never be generated.
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m1_tx_first_wait_clk_l :
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m1_tx_first_wait_clk_l :
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begin
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begin
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ps2_data_hi_z <= 0;
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ps2_data_hi_z <= 0;
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if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
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if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
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else m1_next_state <= m1_tx_first_wait_clk_l;
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else m1_next_state <= m1_tx_first_wait_clk_l;
|
end
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end
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|
|
m1_tx_wait_clk_h :
|
m1_tx_wait_clk_h :
|
begin
|
begin
|
enable_timer_5usec <= 1;
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enable_timer_5usec <= 1;
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ps2_data_hi_z <= q[0];
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ps2_data_hi_z <= q[0];
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if (ps2_clk_s && timer_5usec_done)
|
if (ps2_clk_s && timer_5usec_done)
|
m1_next_state <= m1_tx_rising_edge_marker;
|
m1_next_state <= m1_tx_rising_edge_marker;
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else
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else
|
m1_next_state <= m1_tx_wait_clk_h;
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m1_next_state <= m1_tx_wait_clk_h;
|
end
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end
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|
|
m1_tx_rising_edge_marker :
|
m1_tx_rising_edge_marker :
|
begin
|
begin
|
ps2_data_hi_z <= q[0];
|
ps2_data_hi_z <= q[0];
|
m1_next_state <= m1_tx_clk_h;
|
m1_next_state <= m1_tx_clk_h;
|
end
|
end
|
|
|
m1_tx_clk_h :
|
m1_tx_clk_h :
|
begin
|
begin
|
ps2_data_hi_z <= q[0];
|
ps2_data_hi_z <= q[0];
|
if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;
|
if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;
|
else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
|
else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
|
else m1_next_state <= m1_tx_clk_h;
|
else m1_next_state <= m1_tx_clk_h;
|
end
|
end
|
|
|
m1_tx_clk_l :
|
m1_tx_clk_l :
|
begin
|
begin
|
ps2_data_hi_z <= q[0];
|
ps2_data_hi_z <= q[0];
|
if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;
|
if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;
|
else m1_next_state <= m1_tx_clk_l;
|
else m1_next_state <= m1_tx_clk_l;
|
end
|
end
|
|
|
m1_tx_wait_keyboard_ack :
|
m1_tx_wait_keyboard_ack :
|
begin
|
begin
|
if (~ps2_clk_s && ps2_data_s)
|
if (~ps2_clk_s && ps2_data_s)
|
m1_next_state <= m1_tx_error_no_keyboard_ack;
|
m1_next_state <= m1_tx_error_no_keyboard_ack;
|
else if (~ps2_clk_s && ~ps2_data_s)
|
else if (~ps2_clk_s && ~ps2_data_s)
|
m1_next_state <= m1_tx_done_recovery;
|
m1_next_state <= m1_tx_done_recovery;
|
else m1_next_state <= m1_tx_wait_keyboard_ack;
|
else m1_next_state <= m1_tx_wait_keyboard_ack;
|
end
|
end
|
|
|
m1_tx_done_recovery :
|
m1_tx_done_recovery :
|
begin
|
begin
|
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
|
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
|
else m1_next_state <= m1_tx_done_recovery;
|
else m1_next_state <= m1_tx_done_recovery;
|
end
|
end
|
|
|
m1_tx_error_no_keyboard_ack :
|
m1_tx_error_no_keyboard_ack :
|
begin
|
begin
|
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
|
if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
|
else m1_next_state <= m1_tx_error_no_keyboard_ack;
|
else m1_next_state <= m1_tx_error_no_keyboard_ack;
|
end
|
end
|
|
|
default : m1_next_state <= m1_rx_clk_h;
|
default : m1_next_state <= m1_rx_clk_h;
|
endcase
|
endcase
|
end
|
end
|
|
|
// State register
|
// State register
|
always @(posedge wb_clk_i)
|
always @(posedge wb_clk_i)
|
begin : m1_state_register
|
begin : m1_state_register
|
if (wb_rst_i) m1_state <= m1_rx_clk_h;
|
if (wb_rst_i) m1_state <= m1_rx_clk_h;
|
else m1_state <= m1_next_state;
|
else m1_state <= m1_next_state;
|
end
|
end
|
|
|
// wb_dat_o - scancode
|
// wb_dat_o - scancode
|
always @(posedge wb_clk_i)
|
always @(posedge wb_clk_i)
|
if (wb_rst_i) wb_dat_o <= 8'b0;
|
if (wb_rst_i) wb_dat_o <= 8'b0;
|
else wb_dat_o <=
|
else wb_dat_o <=
|
(rx_output_strobe && q[8:1]) ? (q[8] ? q[8:1]
|
(rx_output_strobe && q[8:1]) ? (q[8] ? q[8:1]
|
: {hold_released,xt_code})
|
: {hold_released,xt_code})
|
: wb_dat_o;
|
: wb_dat_o;
|
|
|
// This is the bit counter
|
// This is the bit counter
|
always @(posedge wb_clk_i)
|
always @(posedge wb_clk_i)
|
begin
|
begin
|
if (wb_rst_i
|
if (wb_rst_i
|
|| rx_shifting_done
|
|| rx_shifting_done
|
|| (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.
|
|| (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.
|
) bit_count <= 0; // normal reset
|
) bit_count <= 0; // normal reset
|
else if (timer_60usec_done
|
else if (timer_60usec_done
|
&& (m1_state == m1_rx_clk_h)
|
&& (m1_state == m1_rx_clk_h)
|
&& (ps2_clk_s)
|
&& (ps2_clk_s)
|
) bit_count <= 0; // rx watchdog timer reset
|
) bit_count <= 0; // rx watchdog timer reset
|
else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx
|
else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx
|
||(m1_state == m1_tx_rising_edge_marker) // increment for tx
|
||(m1_state == m1_tx_rising_edge_marker) // increment for tx
|
)
|
)
|
bit_count <= bit_count + 1;
|
bit_count <= bit_count + 1;
|
end
|
end
|
|
|
// Store the special scan code status bits
|
// Store the special scan code status bits
|
// Not the final output, but an intermediate storage place,
|
// Not the final output, but an intermediate storage place,
|
// until the entire set of output data can be assembled.
|
// until the entire set of output data can be assembled.
|
always @(posedge wb_clk_i)
|
always @(posedge wb_clk_i)
|
if (wb_rst_i || rx_output_event) hold_released <= 0;
|
if (wb_rst_i || rx_output_event) hold_released <= 0;
|
else if (rx_shifting_done && released) hold_released <= 1;
|
else if (rx_shifting_done && released) hold_released <= 1;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module translate_8042 (
|
module translate_8042 (
|
input [6:0] at_code,
|
input [6:0] at_code,
|
output reg [6:0] xt_code
|
output reg [6:0] xt_code
|
);
|
);
|
|
|
// Behaviour
|
// Behaviour
|
always @(at_code)
|
always @(at_code)
|
case (at_code)
|
case (at_code)
|
7'h00: xt_code <= 7'h7f;
|
7'h00: xt_code <= 7'h7f;
|
7'h01: xt_code <= 7'h43;
|
7'h01: xt_code <= 7'h43;
|
7'h02: xt_code <= 7'h41;
|
7'h02: xt_code <= 7'h41;
|
7'h03: xt_code <= 7'h3f;
|
7'h03: xt_code <= 7'h3f;
|
7'h04: xt_code <= 7'h3d;
|
7'h04: xt_code <= 7'h3d;
|
7'h05: xt_code <= 7'h3b;
|
7'h05: xt_code <= 7'h3b;
|
7'h06: xt_code <= 7'h3c;
|
7'h06: xt_code <= 7'h3c;
|
7'h07: xt_code <= 7'h58;
|
7'h07: xt_code <= 7'h58;
|
7'h08: xt_code <= 7'h64;
|
7'h08: xt_code <= 7'h64;
|
7'h09: xt_code <= 7'h44;
|
7'h09: xt_code <= 7'h44;
|
7'h0a: xt_code <= 7'h42;
|
7'h0a: xt_code <= 7'h42;
|
7'h0b: xt_code <= 7'h40;
|
7'h0b: xt_code <= 7'h40;
|
7'h0c: xt_code <= 7'h3e;
|
7'h0c: xt_code <= 7'h3e;
|
7'h0d: xt_code <= 7'h0f;
|
7'h0d: xt_code <= 7'h0f;
|
7'h0e: xt_code <= 7'h29;
|
7'h0e: xt_code <= 7'h29;
|
7'h0f: xt_code <= 7'h59;
|
7'h0f: xt_code <= 7'h59;
|
7'h10: xt_code <= 7'h65;
|
7'h10: xt_code <= 7'h65;
|
7'h11: xt_code <= 7'h38;
|
7'h11: xt_code <= 7'h38;
|
7'h12: xt_code <= 7'h2a;
|
7'h12: xt_code <= 7'h2a;
|
7'h13: xt_code <= 7'h70;
|
7'h13: xt_code <= 7'h70;
|
7'h14: xt_code <= 7'h1d;
|
7'h14: xt_code <= 7'h1d;
|
7'h15: xt_code <= 7'h10;
|
7'h15: xt_code <= 7'h10;
|
7'h16: xt_code <= 7'h02;
|
7'h16: xt_code <= 7'h02;
|
7'h17: xt_code <= 7'h5a;
|
7'h17: xt_code <= 7'h5a;
|
7'h18: xt_code <= 7'h66;
|
7'h18: xt_code <= 7'h66;
|
7'h19: xt_code <= 7'h71;
|
7'h19: xt_code <= 7'h71;
|
7'h1a: xt_code <= 7'h2c;
|
7'h1a: xt_code <= 7'h2c;
|
7'h1b: xt_code <= 7'h1f;
|
7'h1b: xt_code <= 7'h1f;
|
7'h1c: xt_code <= 7'h1e;
|
7'h1c: xt_code <= 7'h1e;
|
7'h1d: xt_code <= 7'h11;
|
7'h1d: xt_code <= 7'h11;
|
7'h1e: xt_code <= 7'h03;
|
7'h1e: xt_code <= 7'h03;
|
7'h1f: xt_code <= 7'h5b;
|
7'h1f: xt_code <= 7'h5b;
|
7'h20: xt_code <= 7'h67;
|
7'h20: xt_code <= 7'h67;
|
7'h21: xt_code <= 7'h2e;
|
7'h21: xt_code <= 7'h2e;
|
7'h22: xt_code <= 7'h2d;
|
7'h22: xt_code <= 7'h2d;
|
7'h23: xt_code <= 7'h20;
|
7'h23: xt_code <= 7'h20;
|
7'h24: xt_code <= 7'h12;
|
7'h24: xt_code <= 7'h12;
|
7'h25: xt_code <= 7'h05;
|
7'h25: xt_code <= 7'h05;
|
7'h26: xt_code <= 7'h04;
|
7'h26: xt_code <= 7'h04;
|
7'h27: xt_code <= 7'h5c;
|
7'h27: xt_code <= 7'h5c;
|
7'h28: xt_code <= 7'h68;
|
7'h28: xt_code <= 7'h68;
|
7'h29: xt_code <= 7'h39;
|
7'h29: xt_code <= 7'h39;
|
7'h2a: xt_code <= 7'h2f;
|
7'h2a: xt_code <= 7'h2f;
|
7'h2b: xt_code <= 7'h21;
|
7'h2b: xt_code <= 7'h21;
|
7'h2c: xt_code <= 7'h14;
|
7'h2c: xt_code <= 7'h14;
|
7'h2d: xt_code <= 7'h13;
|
7'h2d: xt_code <= 7'h13;
|
7'h2e: xt_code <= 7'h06;
|
7'h2e: xt_code <= 7'h06;
|
7'h2f: xt_code <= 7'h5d;
|
7'h2f: xt_code <= 7'h5d;
|
7'h30: xt_code <= 7'h69;
|
7'h30: xt_code <= 7'h69;
|
7'h31: xt_code <= 7'h31;
|
7'h31: xt_code <= 7'h31;
|
7'h32: xt_code <= 7'h30;
|
7'h32: xt_code <= 7'h30;
|
7'h33: xt_code <= 7'h23;
|
7'h33: xt_code <= 7'h23;
|
7'h34: xt_code <= 7'h22;
|
7'h34: xt_code <= 7'h22;
|
7'h35: xt_code <= 7'h15;
|
7'h35: xt_code <= 7'h15;
|
7'h36: xt_code <= 7'h07;
|
7'h36: xt_code <= 7'h07;
|
7'h37: xt_code <= 7'h5e;
|
7'h37: xt_code <= 7'h5e;
|
7'h38: xt_code <= 7'h6a;
|
7'h38: xt_code <= 7'h6a;
|
7'h39: xt_code <= 7'h72;
|
7'h39: xt_code <= 7'h72;
|
7'h3a: xt_code <= 7'h32;
|
7'h3a: xt_code <= 7'h32;
|
7'h3b: xt_code <= 7'h24;
|
7'h3b: xt_code <= 7'h24;
|
7'h3c: xt_code <= 7'h16;
|
7'h3c: xt_code <= 7'h16;
|
7'h3d: xt_code <= 7'h08;
|
7'h3d: xt_code <= 7'h08;
|
7'h3e: xt_code <= 7'h09;
|
7'h3e: xt_code <= 7'h09;
|
7'h3f: xt_code <= 7'h5f;
|
7'h3f: xt_code <= 7'h5f;
|
7'h40: xt_code <= 7'h6b;
|
7'h40: xt_code <= 7'h6b;
|
7'h41: xt_code <= 7'h33;
|
7'h41: xt_code <= 7'h33;
|
7'h42: xt_code <= 7'h25;
|
7'h42: xt_code <= 7'h25;
|
7'h43: xt_code <= 7'h17;
|
7'h43: xt_code <= 7'h17;
|
7'h44: xt_code <= 7'h18;
|
7'h44: xt_code <= 7'h18;
|
7'h45: xt_code <= 7'h0b;
|
7'h45: xt_code <= 7'h0b;
|
7'h46: xt_code <= 7'h0a;
|
7'h46: xt_code <= 7'h0a;
|
7'h47: xt_code <= 7'h60;
|
7'h47: xt_code <= 7'h60;
|
7'h48: xt_code <= 7'h6c;
|
7'h48: xt_code <= 7'h6c;
|
7'h49: xt_code <= 7'h34;
|
7'h49: xt_code <= 7'h34;
|
7'h4a: xt_code <= 7'h35;
|
7'h4a: xt_code <= 7'h35;
|
7'h4b: xt_code <= 7'h26;
|
7'h4b: xt_code <= 7'h26;
|
7'h4c: xt_code <= 7'h27;
|
7'h4c: xt_code <= 7'h27;
|
7'h4d: xt_code <= 7'h19;
|
7'h4d: xt_code <= 7'h19;
|
7'h4e: xt_code <= 7'h0c;
|
7'h4e: xt_code <= 7'h0c;
|
7'h4f: xt_code <= 7'h61;
|
7'h4f: xt_code <= 7'h61;
|
7'h50: xt_code <= 7'h6d;
|
7'h50: xt_code <= 7'h6d;
|
7'h51: xt_code <= 7'h73;
|
7'h51: xt_code <= 7'h73;
|
7'h52: xt_code <= 7'h28;
|
7'h52: xt_code <= 7'h28;
|
7'h53: xt_code <= 7'h74;
|
7'h53: xt_code <= 7'h74;
|
7'h54: xt_code <= 7'h1a;
|
7'h54: xt_code <= 7'h1a;
|
7'h55: xt_code <= 7'h0d;
|
7'h55: xt_code <= 7'h0d;
|
7'h56: xt_code <= 7'h62;
|
7'h56: xt_code <= 7'h62;
|
7'h57: xt_code <= 7'h6e;
|
7'h57: xt_code <= 7'h6e;
|
7'h58: xt_code <= 7'h3a;
|
7'h58: xt_code <= 7'h3a;
|
7'h59: xt_code <= 7'h36;
|
7'h59: xt_code <= 7'h36;
|
7'h5a: xt_code <= 7'h1c;
|
7'h5a: xt_code <= 7'h1c;
|
7'h5b: xt_code <= 7'h1b;
|
7'h5b: xt_code <= 7'h1b;
|
7'h5c: xt_code <= 7'h75;
|
7'h5c: xt_code <= 7'h75;
|
7'h5d: xt_code <= 7'h2b;
|
7'h5d: xt_code <= 7'h2b;
|
7'h5e: xt_code <= 7'h63;
|
7'h5e: xt_code <= 7'h63;
|
7'h5f: xt_code <= 7'h76;
|
7'h5f: xt_code <= 7'h76;
|
7'h60: xt_code <= 7'h55;
|
7'h60: xt_code <= 7'h55;
|
7'h61: xt_code <= 7'h56;
|
7'h61: xt_code <= 7'h56;
|
7'h62: xt_code <= 7'h77;
|
7'h62: xt_code <= 7'h77;
|
7'h63: xt_code <= 7'h78;
|
7'h63: xt_code <= 7'h78;
|
7'h64: xt_code <= 7'h79;
|
7'h64: xt_code <= 7'h79;
|
7'h65: xt_code <= 7'h7a;
|
7'h65: xt_code <= 7'h7a;
|
7'h66: xt_code <= 7'h0e;
|
7'h66: xt_code <= 7'h0e;
|
7'h67: xt_code <= 7'h7b;
|
7'h67: xt_code <= 7'h7b;
|
7'h68: xt_code <= 7'h7c;
|
7'h68: xt_code <= 7'h7c;
|
7'h69: xt_code <= 7'h4f;
|
7'h69: xt_code <= 7'h4f;
|
7'h6a: xt_code <= 7'h7d;
|
7'h6a: xt_code <= 7'h7d;
|
7'h6b: xt_code <= 7'h4b;
|
7'h6b: xt_code <= 7'h4b;
|
7'h6c: xt_code <= 7'h47;
|
7'h6c: xt_code <= 7'h47;
|
7'h6d: xt_code <= 7'h7e;
|
7'h6d: xt_code <= 7'h7e;
|
7'h6e: xt_code <= 7'h7f;
|
7'h6e: xt_code <= 7'h7f;
|
7'h6f: xt_code <= 7'h6f;
|
7'h6f: xt_code <= 7'h6f;
|
7'h70: xt_code <= 7'h52;
|
7'h70: xt_code <= 7'h52;
|
7'h71: xt_code <= 7'h53;
|
7'h71: xt_code <= 7'h53;
|
7'h72: xt_code <= 7'h50;
|
7'h72: xt_code <= 7'h50;
|
7'h73: xt_code <= 7'h4c;
|
7'h73: xt_code <= 7'h4c;
|
7'h74: xt_code <= 7'h4d;
|
7'h74: xt_code <= 7'h4d;
|
7'h75: xt_code <= 7'h48;
|
7'h75: xt_code <= 7'h48;
|
7'h76: xt_code <= 7'h01;
|
7'h76: xt_code <= 7'h01;
|
7'h77: xt_code <= 7'h45;
|
7'h77: xt_code <= 7'h45;
|
7'h78: xt_code <= 7'h57;
|
7'h78: xt_code <= 7'h57;
|
7'h79: xt_code <= 7'h4e;
|
7'h79: xt_code <= 7'h4e;
|
7'h7a: xt_code <= 7'h51;
|
7'h7a: xt_code <= 7'h51;
|
7'h7b: xt_code <= 7'h4a;
|
7'h7b: xt_code <= 7'h4a;
|
7'h7c: xt_code <= 7'h37;
|
7'h7c: xt_code <= 7'h37;
|
7'h7d: xt_code <= 7'h49;
|
7'h7d: xt_code <= 7'h49;
|
7'h7e: xt_code <= 7'h46;
|
7'h7e: xt_code <= 7'h46;
|
7'h7f: xt_code <= 7'h54;
|
7'h7f: xt_code <= 7'h54;
|
endcase
|
endcase
|
endmodule
|
endmodule
|
|
|