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[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Diff between revs 11 and 27

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///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    zippy_tb.cpp
// Filename:    zippy_tb.cpp
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
//              able to give this program the name of a piece of compiled
//              able to give this program the name of a piece of compiled
//              code to load into memory.  For now, we hand assemble with the
//              code to load into memory.  For now, we hand assemble with the
//              computers help.
//              computers help.
//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Tecnology, LLC
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
//
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
//
//
#include <signal.h>
#include <signal.h>
#include <time.h>
#include <time.h>
#include <unistd.h>
#include <unistd.h>
 
 
#include <ctype.h>
#include <ctype.h>
#include <ncurses.h>
#include <ncurses.h>
 
 
#include "verilated.h"
#include "verilated.h"
#include "Vzipsystem.h"
#include "Vzipsystem.h"
 
 
#include "testb.h"
#include "testb.h"
// #include "twoc.h"
// #include "twoc.h"
// #include "qspiflashsim.h"
// #include "qspiflashsim.h"
#include "memsim.h"
#include "memsim.h"
#include "zopcodes.h"
#include "zopcodes.h"
#include "zparser.h"
#include "zparser.h"
 
 
#define CMD_REG         0
#define CMD_REG         0
#define CMD_DATA        1
#define CMD_DATA        1
#define CMD_HALT        (1<<10)
#define CMD_HALT        (1<<10)
#define CMD_STALL       (1<<9)
#define CMD_STALL       (1<<9)
#define CMD_STEP        (1<<8)
#define CMD_STEP        (1<<8)
#define CMD_INT         (1<<7)
#define CMD_INT         (1<<7)
#define CMD_RESET       (1<<6)
#define CMD_RESET       (1<<6)
 
 
 
 
// No particular "parameters" need definition or redefinition here.
// No particular "parameters" need definition or redefinition here.
class   ZIPPY_TB : public TESTB<Vzipsystem> {
class   ZIPPY_TB : public TESTB<Vzipsystem> {
public:
public:
        unsigned long   m_mem_size;
        unsigned long   m_mem_size;
        MEMSIM          m_mem;
        MEMSIM          m_mem;
        // QSPIFLASHSIM m_flash;
        // QSPIFLASHSIM m_flash;
        FILE            *dbg_fp;
        FILE            *dbg_fp;
        bool            dbg_flag, bomb;
        bool            dbg_flag, bomb;
 
 
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
                //dbg_fp = fopen("dbg.txt", "w");
                //dbg_fp = fopen("dbg.txt", "w");
                dbg_fp = NULL;
                dbg_fp = NULL;
                dbg_flag = false;
                dbg_flag = false;
                bomb = false;
                bomb = false;
        }
        }
 
 
        void    reset(void) {
        void    reset(void) {
                // m_flash.debug(false);
                // m_flash.debug(false);
                TESTB<Vzipsystem>::reset();
                TESTB<Vzipsystem>::reset();
        }
        }
 
 
        bool    on_tick(void) {
        bool    on_tick(void) {
                tick();
                tick();
                return true;
                return true;
        }
        }
 
 
        void    showval(int y, int x, const char *lbl, unsigned int v) {
        void    showval(int y, int x, const char *lbl, unsigned int v) {
                mvprintw(y,x, "%s: 0x%08x", lbl, v);
                mvprintw(y,x, "%s: 0x%08x", lbl, v);
        }
        }
 
 
        void    dispreg(int y, int x, const char *n, unsigned int v) {
        void    dispreg(int y, int x, const char *n, unsigned int v) {
                // 4,4,8,1 = 17 of 20, +3 = 19
                // 4,4,8,1 = 17 of 20, +3 = 19
                mvprintw(y, x, "%s: 0x%08x", n, v);
                mvprintw(y, x, "%s: 0x%08x", n, v);
        }
        }
 
 
        void    showreg(int y, int x, const char *n, int r) {
        void    showreg(int y, int x, const char *n, int r) {
                // 4,4,8,1 = 17 of 20, +3 = 19
                // 4,4,8,1 = 17 of 20, +3 = 19
                mvprintw(y, x, "%s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
                mvprintw(y, x, "%s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
                                &&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
                        ?'a':' ');
                        ?'a':' ');
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
                addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
                                &&(m_core->v__DOT__thecpu__DOT__dcdvalid)
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
                                &&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
                        ?'b':' ');
                        ?'b':' ');
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
                        ?'W':' ');
                        ?'W':' ');
        }
        }
 
 
        void    showins(int y, const char *lbl, const int ce, const int valid,
        void    showins(int y, const char *lbl, const int ce, const int valid,
                        const int gie, const int stall, const unsigned int pc) {
                        const int gie, const int stall, const unsigned int pc) {
                char    line[80];
                char    line[80];
 
 
                if (ce)
                if (ce)
                        mvprintw(y, 0, "Ck ");
                        mvprintw(y, 0, "Ck ");
                else
                else
                        mvprintw(y, 0, "   ");
                        mvprintw(y, 0, "   ");
                if (stall)
                if (stall)
                        printw("Stl ");
                        printw("Stl ");
                else
                else
                        printw("    ");
                        printw("    ");
                printw("%s: 0x%08x", lbl, pc);
                printw("%s: 0x%08x", lbl, pc);
 
 
                if (valid) {
                if (valid) {
                        if (gie) attroff(A_BOLD);
                        if (gie) attroff(A_BOLD);
                        else    attron(A_BOLD);
                        else    attron(A_BOLD);
                        zipi_to_string(m_mem[pc], line);
                        zipi_to_string(m_mem[pc], line);
                        printw("  %-20s", &line[1]);
                        printw("  %-24s", &line[1]);
                } else {
                } else {
                        attroff(A_BOLD);
                        attroff(A_BOLD);
                        printw("  (0x%08x)%28s", m_mem[pc],"");
                        printw("  (0x%08x)%28s", m_mem[pc],"");
                }
                }
                attroff(A_BOLD);
                attroff(A_BOLD);
        }
        }
 
 
        void    dbgins(const char *lbl, const int ce, const int valid,
        void    dbgins(const char *lbl, const int ce, const int valid,
                        const int gie, const int stall, const unsigned int pc) {
                        const int gie, const int stall, const unsigned int pc) {
                char    line[80];
                char    line[80];
 
 
                if (!dbg_fp)
                if (!dbg_fp)
                        return;
                        return;
 
 
                if (ce)
                if (ce)
                        fprintf(dbg_fp, "%s Ck ", lbl);
                        fprintf(dbg_fp, "%s Ck ", lbl);
                else
                else
                        fprintf(dbg_fp, "%s    ", lbl);
                        fprintf(dbg_fp, "%s    ", lbl);
                if (stall)
                if (stall)
                        fprintf(dbg_fp, "Stl ");
                        fprintf(dbg_fp, "Stl ");
                else
                else
                        fprintf(dbg_fp, "    ");
                        fprintf(dbg_fp, "    ");
                fprintf(dbg_fp, "0x%08x:  ", pc);
                fprintf(dbg_fp, "0x%08x:  ", pc);
 
 
                if (valid) {
                if (valid) {
                        zipi_to_string(m_mem[pc], line);
                        zipi_to_string(m_mem[pc], line);
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
                        fprintf(dbg_fp, "  %-20s\n", &line[1]);
                } else {
                } else {
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
                        fprintf(dbg_fp, "  (0x%08x)\n", m_mem[pc]);
                }
                }
        }
        }
 
 
        void    show_state(void) {
        void    show_state(void) {
                int     ln= 0;
                int     ln= 0;
 
 
                mvprintw(ln,0, "Peripherals-SS"); ln++;
                mvprintw(ln,0, "Peripherals-SS"); ln++;
                /*
                /*
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
                        mvprintw(ln, 17, "%s%s",
                        mvprintw(ln, 17, "%s%s",
                                ((m_core->v__DOT__sys_cyc)
                                ((m_core->v__DOT__sys_cyc)
                                &&(m_core->v__DOT__sys_we)
                                &&(m_core->v__DOT__sys_we)
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
                                &&(m_core->v__DOT__sys_addr == 0))?"W":" ",
                                (m_core->v__DOT__trap_int)?"I":" ");
                                (m_core->v__DOT__trap_int)?"I":" ");
                */
                */
                showval(ln, 1, "PIC ", m_core->v__DOT__pic_data);
                showval(ln, 1, "PIC ", m_core->v__DOT__pic_data);
                showval(ln,21, "WDT ", m_core->v__DOT__watchdog__DOT__r_value);
                showval(ln,21, "WDT ", m_core->v__DOT__watchdog__DOT__r_value);
                showval(ln,41, "CACH", m_core->v__DOT__manualcache__DOT__cache_base);
                showval(ln,41, "CACH", m_core->v__DOT__manualcache__DOT__cache_base);
                showval(ln,61, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state);
                showval(ln,61, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state);
 
 
                ln++;
                ln++;
                showval(ln, 1, "TMRA", m_core->v__DOT__timer_a__DOT__r_value);
                showval(ln, 1, "TMRA", m_core->v__DOT__timer_a__DOT__r_value);
                showval(ln,21, "TMRB", m_core->v__DOT__timer_b__DOT__r_value);
                showval(ln,21, "TMRB", m_core->v__DOT__timer_b__DOT__r_value);
                showval(ln,41, "TMRB", m_core->v__DOT__timer_c__DOT__r_value);
                showval(ln,41, "TMRB", m_core->v__DOT__timer_c__DOT__r_value);
                showval(ln,61, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter);
                showval(ln,61, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter);
 
 
                ln++;
                ln++;
                showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
                showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
                showval(ln,21, "UOST", m_core->v__DOT__uoc_data);
                showval(ln,21, "UOST", m_core->v__DOT__uoc_data);
                showval(ln,41, "UPST", m_core->v__DOT__upc_data);
                showval(ln,41, "UPST", m_core->v__DOT__upc_data);
                showval(ln,61, "UICT", m_core->v__DOT__uic_data);
                showval(ln,61, "UICT", m_core->v__DOT__uic_data);
 
 
                ln++;
                ln++;
                mvprintw(ln, 40, "%s %s",
                mvprintw(ln, 40, "%s %s",
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
                mvprintw(ln, 40, "%s %s %s 0x%02x",
                mvprintw(ln, 40, "%s %s %s 0x%02x",
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
                        (m_core->v__DOT__cmd_addr)&0x3f);
                        (m_core->v__DOT__cmd_addr)&0x3f);
                if (m_core->v__DOT__thecpu__DOT__gie)
                if (m_core->v__DOT__thecpu__DOT__gie)
                        attroff(A_BOLD);
                        attroff(A_BOLD);
                else
                else
                        attron(A_BOLD);
                        attron(A_BOLD);
                mvprintw(ln, 0, "Supervisor Registers");
                mvprintw(ln, 0, "Supervisor Registers");
                ln++;
                ln++;
 
 
                showreg(ln, 1, "sR0 ", 0);
                showreg(ln, 1, "sR0 ", 0);
                showreg(ln,21, "sR1 ", 1);
                showreg(ln,21, "sR1 ", 1);
                showreg(ln,41, "sR2 ", 2);
                showreg(ln,41, "sR2 ", 2);
                showreg(ln,61, "sR3 ", 3); ln++;
                showreg(ln,61, "sR3 ", 3); ln++;
 
 
                showreg(ln, 1, "sR4 ", 4);
                showreg(ln, 1, "sR4 ", 4);
                showreg(ln,21, "sR5 ", 5);
                showreg(ln,21, "sR5 ", 5);
                showreg(ln,41, "sR6 ", 6);
                showreg(ln,41, "sR6 ", 6);
                showreg(ln,61, "sR7 ", 7); ln++;
                showreg(ln,61, "sR7 ", 7); ln++;
 
 
                showreg(ln, 1, "sR8 ",  8);
                showreg(ln, 1, "sR8 ",  8);
                showreg(ln,21, "sR9 ",  9);
                showreg(ln,21, "sR9 ",  9);
                showreg(ln,41, "sR10", 10);
                showreg(ln,41, "sR10", 10);
                showreg(ln,61, "sR11", 11); ln++;
                showreg(ln,61, "sR11", 11); ln++;
 
 
                showreg(ln, 1, "sR12", 12);
                showreg(ln, 1, "sR12", 12);
                showreg(ln,21, "sSP ", 13);
                showreg(ln,21, "sSP ", 13);
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s%s",
 
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":"   ",
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":"   ",
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":"   ",
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":"   ",
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
                        (m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
                mvprintw(ln,61, "sPC : 0x%08x", m_core->v__DOT__thecpu__DOT__ipc);
                mvprintw(ln,61, "sPC : 0x%08x", m_core->v__DOT__thecpu__DOT__ipc);
                ln++;
                ln++;
 
 
                if (m_core->v__DOT__thecpu__DOT__gie)
                if (m_core->v__DOT__thecpu__DOT__gie)
                        attron(A_BOLD);
                        attron(A_BOLD);
                else
                else
                        attroff(A_BOLD);
                        attroff(A_BOLD);
                mvprintw(ln, 0, "User Registers"); ln++;
                mvprintw(ln, 0, "User Registers"); ln++;
                showreg(ln, 1, "uR0 ", 16);
                showreg(ln, 1, "uR0 ", 16);
                showreg(ln,21, "uR1 ", 17);
                showreg(ln,21, "uR1 ", 17);
                showreg(ln,41, "uR2 ", 18);
                showreg(ln,41, "uR2 ", 18);
                showreg(ln,61, "uR3 ", 19); ln++;
                showreg(ln,61, "uR3 ", 19); ln++;
 
 
                showreg(ln, 1, "uR4 ", 20);
                showreg(ln, 1, "uR4 ", 20);
                showreg(ln,21, "uR5 ", 21);
                showreg(ln,21, "uR5 ", 21);
                showreg(ln,41, "uR6 ", 22);
                showreg(ln,41, "uR6 ", 22);
                showreg(ln,61, "uR7 ", 23); ln++;
                showreg(ln,61, "uR7 ", 23); ln++;
 
 
                showreg(ln, 1, "uR8 ", 24);
                showreg(ln, 1, "uR8 ", 24);
                showreg(ln,21, "uR9 ", 25);
                showreg(ln,21, "uR9 ", 25);
                showreg(ln,41, "uR10", 26);
                showreg(ln,41, "uR10", 26);
                showreg(ln,61, "uR11", 27); ln++;
                showreg(ln,61, "uR11", 27); ln++;
 
 
                showreg(ln, 1, "uR12", 28);
                showreg(ln, 1, "uR12", 28);
                showreg(ln,21, "uSP ", 29);
                showreg(ln,21, "uSP ", 29);
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s%s",
 
                        (m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":"   ",
                        (m_core->v__DOT__thecpu__DOT__step)?"STP":"   ",
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":"   ",
                        (m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":"   ",
                        (m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
                        (m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
                        (m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
                        (m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
                        (m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
                mvprintw(ln,61, "uPC : 0x%08x", m_core->v__DOT__thecpu__DOT__upc);
                mvprintw(ln,61, "uPC : 0x%08x", m_core->v__DOT__thecpu__DOT__upc);
 
 
                attroff(A_BOLD);
                attroff(A_BOLD);
                ln+=1;
                ln+=1;
 
 
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d",
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d",
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting);
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting);
                ln++;
                ln++;
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
                        (m_core->v__DOT__wb_data)); ln++;
                        (m_core->v__DOT__wb_data)); ln++;
 
 
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                        (m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
                        (m_core->v__DOT__thecpu__DOT__mem_data),
                        (m_core->v__DOT__thecpu__DOT__mem_data),
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
                        (m_core->v__DOT__cpu_stall)?"STL":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
                        (m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
 
 
                mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                        (m_core->o_wb_cyc)?"CYC":"   ",
                        (m_core->o_wb_cyc)?"CYC":"   ",
                        (m_core->o_wb_stb)?"STB":"   ",
                        (m_core->o_wb_stb)?"STB":"   ",
                        (m_core->o_wb_we )?"WE":"  ",
                        (m_core->o_wb_we )?"WE":"  ",
                        (m_core->o_wb_addr),
                        (m_core->o_wb_addr),
                        (m_core->o_wb_data),
                        (m_core->o_wb_data),
                        (m_core->i_wb_ack)?"ACK":"   ",
                        (m_core->i_wb_ack)?"ACK":"   ",
                        (m_core->i_wb_stall)?"STL":"   ",
                        (m_core->i_wb_stall)?"STL":"   ",
                        (m_core->i_wb_data)); ln+=2;
                        (m_core->i_wb_data)); ln+=2;
 
 
                showins(ln, "I ",
                showins(ln, "I ",
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__pf_valid,
                        m_core->v__DOT__thecpu__DOT__pf_valid,
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
                        m_core->v__DOT__thecpu__DOT__gie,
                        m_core->v__DOT__thecpu__DOT__gie,
                        0,
                        0,
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
 
 
                showins(ln, "Dc",
                showins(ln, "Dc",
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
 
 
                showins(ln, "Op",
                showins(ln, "Op",
                        m_core->v__DOT__thecpu__DOT__op_ce,
                        m_core->v__DOT__thecpu__DOT__op_ce,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
 
 
                showins(ln, "Al",
                showins(ln, "Al",
                        m_core->v__DOT__thecpu__DOT__alu_ce,
                        m_core->v__DOT__thecpu__DOT__alu_ce,
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                        m_core->v__DOT__thecpu__DOT__alu_gie,
                        m_core->v__DOT__thecpu__DOT__alu_gie,
                        m_core->v__DOT__thecpu__DOT__alu_stall,
                        m_core->v__DOT__thecpu__DOT__alu_stall,
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
 
 
 
                mvprintw(ln-5, 48,"%s %s",
 
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
 
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
                mvprintw(ln-4, 48,
                mvprintw(ln-4, 48,
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
                printw("(%s:%02x,%x)",
                printw("(%s:%02x,%x)",
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
                        (m_core->v__DOT__thecpu__DOT__opF&0x0ff),
                        (m_core->v__DOT__thecpu__DOT__op_gie)
                        (m_core->v__DOT__thecpu__DOT__op_gie)
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
 
 
                printw("(%s%s%s:%02x)",
                printw("(%s%s%s:%02x)",
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
                        (m_core->v__DOT__thecpu__DOT__opF_wr)?"OF":"  ",
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
                        (m_core->v__DOT__thecpu__DOT__alF_wr)?"FL":"  ",
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
                /*
                /*
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
                mvprintw(ln-3, 48, "dcdI : 0x%08x",
                        m_core->v__DOT__thecpu__DOT__dcdI);
                        m_core->v__DOT__thecpu__DOT__dcdI);
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
                mvprintw(ln-2, 48, "r_opB: 0x%08x",
                        m_core->v__DOT__thecpu__DOT__opB);
                        m_core->v__DOT__thecpu__DOT__opB);
                */
                */
                mvprintw(ln-3, 48, "Op(%x)%8x %8x->%08x",
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
                        m_core->v__DOT__thecpu__DOT__opn,
                        m_core->v__DOT__thecpu__DOT__opn,
                        m_core->v__DOT__thecpu__DOT__opA,
                        m_core->v__DOT__thecpu__DOT__r_opA,
                        m_core->v__DOT__thecpu__DOT__opB,
                        m_core->v__DOT__thecpu__DOT__r_opB);
                        m_core->v__DOT__thecpu__DOT__alu_result);
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
 
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
 
                else
 
                        printw("%8s","");
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
                        (m_core->v__DOT__thecpu__DOT__opM)?"M":" ",
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":"    ",
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":"    ",
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
        }
        }
 
 
        unsigned int    cmd_read(unsigned int a) {
        unsigned int    cmd_read(unsigned int a) {
                if (dbg_fp) {
                if (dbg_fp) {
                        dbg_flag= true;
                        dbg_flag= true;
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
                        fprintf(dbg_fp, "CMD-READ(%d)\n", a);
                }
                }
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
                while((wb_read(CMD_REG) & CMD_STALL) == 0)
                        ;
                        ;
                unsigned int v = wb_read(CMD_DATA);
                unsigned int v = wb_read(CMD_DATA);
 
 
                if (dbg_flag)
                if (dbg_flag)
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
                        fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
                                v);
                                v);
                dbg_flag = false;
                dbg_flag = false;
                return v;
                return v;
        }
        }
 
 
 
        bool    halted(void) {
 
                return (m_core->v__DOT__cmd_halt != 0);
 
        }
 
 
        void    read_state(void) {
        void    read_state(void) {
                int     ln= 0;
                int     ln= 0;
 
 
                mvprintw(ln,0, "Peripherals-RS"); ln++;
                mvprintw(ln,0, "Peripherals-RS"); ln++;
                showval(ln, 1, "PIC ", cmd_read(32+ 0));
                showval(ln, 1, "PIC ", cmd_read(32+ 0));
                showval(ln,21, "WDT ", cmd_read(32+ 1));
                showval(ln,21, "WDT ", cmd_read(32+ 1));
                showval(ln,41, "CACH", cmd_read(32+ 2));
                showval(ln,41, "CACH", cmd_read(32+ 2));
                showval(ln,61, "PIC2", cmd_read(32+ 3));
                showval(ln,61, "PIC2", cmd_read(32+ 3));
                ln++;
                ln++;
                showval(ln, 1, "TMRA", cmd_read(32+ 4));
                showval(ln, 1, "TMRA", cmd_read(32+ 4));
                showval(ln,21, "TMRB", cmd_read(32+ 5));
                showval(ln,21, "TMRB", cmd_read(32+ 5));
                showval(ln,41, "TMRC", cmd_read(32+ 6));
                showval(ln,41, "TMRC", cmd_read(32+ 6));
                showval(ln,61, "JIF ", cmd_read(32+ 7));
                showval(ln,61, "JIF ", cmd_read(32+ 7));
 
 
                ln++;
                ln++;
                showval(ln, 1, "UTSK", cmd_read(32+12));
                showval(ln, 1, "UTSK", cmd_read(32+12));
                showval(ln,21, "UMST", cmd_read(32+13));
                showval(ln,21, "UMST", cmd_read(32+13));
                showval(ln,41, "UPST", cmd_read(32+14));
                showval(ln,41, "UPST", cmd_read(32+14));
                showval(ln,61, "UAST", cmd_read(32+15));
                showval(ln,61, "UAST", cmd_read(32+15));
 
 
                ln++;
                ln++;
                ln++;
                ln++;
                unsigned int cc = cmd_read(14);
                unsigned int cc = cmd_read(14);
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
                if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
                        m_core->v__DOT__thecpu__DOT__gie);
                        m_core->v__DOT__thecpu__DOT__gie);
                if (cc & 0x020)
                if (cc & 0x020)
                        attroff(A_BOLD);
                        attroff(A_BOLD);
                else
                else
                        attron(A_BOLD);
                        attron(A_BOLD);
                mvprintw(ln, 0, "Supervisor Registers");
                mvprintw(ln, 0, "Supervisor Registers");
                ln++;
                ln++;
 
 
                dispreg(ln, 1, "sR0 ", cmd_read(0));
                dispreg(ln, 1, "sR0 ", cmd_read(0));
                dispreg(ln,21, "sR1 ", cmd_read(1));
                dispreg(ln,21, "sR1 ", cmd_read(1));
                dispreg(ln,41, "sR2 ", cmd_read(2));
                dispreg(ln,41, "sR2 ", cmd_read(2));
                dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
                dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
 
 
                dispreg(ln, 1, "sR4 ", cmd_read(4));
                dispreg(ln, 1, "sR4 ", cmd_read(4));
                dispreg(ln,21, "sR5 ", cmd_read(5));
                dispreg(ln,21, "sR5 ", cmd_read(5));
                dispreg(ln,41, "sR6 ", cmd_read(6));
                dispreg(ln,41, "sR6 ", cmd_read(6));
                dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
                dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
 
 
                dispreg(ln, 1, "sR8 ", cmd_read( 8));
                dispreg(ln, 1, "sR8 ", cmd_read( 8));
                dispreg(ln,21, "sR9 ", cmd_read( 9));
                dispreg(ln,21, "sR9 ", cmd_read( 9));
                dispreg(ln,41, "sR10", cmd_read(10));
                dispreg(ln,41, "sR10", cmd_read(10));
                dispreg(ln,61, "sR11", cmd_read(11)); ln++;
                dispreg(ln,61, "sR11", cmd_read(11)); ln++;
 
 
                dispreg(ln, 1, "sR12", cmd_read(12));
                dispreg(ln, 1, "sR12", cmd_read(12));
                dispreg(ln,21, "sSP ", cmd_read(13));
                dispreg(ln,21, "sSP ", cmd_read(13));
 
 
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
                        (cc & 0x040)?"STP":"   ",
                        (cc & 0x040)?"STP":"   ",
                        (cc & 0x020)?"GIE":"   ",
                        (cc & 0x020)?"GIE":"   ",
                        (cc & 0x010)?"SLP":"   ",
                        (cc & 0x010)?"SLP":"   ",
                        (cc&8)?"V":" ",
                        (cc&8)?"V":" ",
                        (cc&4)?"N":" ",
                        (cc&4)?"N":" ",
                        (cc&2)?"C":" ",
                        (cc&2)?"C":" ",
                        (cc&1)?"Z":" ");
                        (cc&1)?"Z":" ");
                mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
                mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
                ln++;
                ln++;
 
 
                if (cc & 0x020)
                if (cc & 0x020)
                        attron(A_BOLD);
                        attron(A_BOLD);
                else
                else
                        attroff(A_BOLD);
                        attroff(A_BOLD);
                mvprintw(ln, 0, "User Registers"); ln++;
                mvprintw(ln, 0, "User Registers"); ln++;
                dispreg(ln, 1, "uR0 ", cmd_read(16));
                dispreg(ln, 1, "uR0 ", cmd_read(16));
                dispreg(ln,21, "uR1 ", cmd_read(17));
                dispreg(ln,21, "uR1 ", cmd_read(17));
                dispreg(ln,41, "uR2 ", cmd_read(18));
                dispreg(ln,41, "uR2 ", cmd_read(18));
                dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
                dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
 
 
                dispreg(ln, 1, "uR4 ", cmd_read(20));
                dispreg(ln, 1, "uR4 ", cmd_read(20));
                dispreg(ln,21, "uR5 ", cmd_read(21));
                dispreg(ln,21, "uR5 ", cmd_read(21));
                dispreg(ln,41, "uR6 ", cmd_read(22));
                dispreg(ln,41, "uR6 ", cmd_read(22));
                dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
                dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
 
 
                dispreg(ln, 1, "uR8 ", cmd_read(24));
                dispreg(ln, 1, "uR8 ", cmd_read(24));
                dispreg(ln,21, "uR9 ", cmd_read(25));
                dispreg(ln,21, "uR9 ", cmd_read(25));
                dispreg(ln,41, "uR10", cmd_read(26));
                dispreg(ln,41, "uR10", cmd_read(26));
                dispreg(ln,61, "uR11", cmd_read(27)); ln++;
                dispreg(ln,61, "uR11", cmd_read(27)); ln++;
 
 
                dispreg(ln, 1, "uR12", cmd_read(28));
                dispreg(ln, 1, "uR12", cmd_read(28));
                dispreg(ln,21, "uSP ", cmd_read(29));
                dispreg(ln,21, "uSP ", cmd_read(29));
                cc = cmd_read(30);
                cc = cmd_read(30);
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
                        (cc&0x040)?"STP":"   ",
                        (cc&0x040)?"STP":"   ",
                        (cc&0x020)?"GIE":"   ",
                        (cc&0x020)?"GIE":"   ",
                        (cc&0x010)?"SLP":"   ",
                        (cc&0x010)?"SLP":"   ",
                        (cc&8)?"V":" ",
                        (cc&8)?"V":" ",
                        (cc&4)?"N":" ",
                        (cc&4)?"N":" ",
                        (cc&2)?"C":" ",
                        (cc&2)?"C":" ",
                        (cc&1)?"Z":" ");
                        (cc&1)?"Z":" ");
                mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
                mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
 
 
                attroff(A_BOLD);
                attroff(A_BOLD);
                ln+=2;
                ln+=2;
 
 
                ln+=3;
                ln+=3;
 
 
                showins(ln, "I ",
                showins(ln, "I ",
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__pf_valid,
                        m_core->v__DOT__thecpu__DOT__pf_valid,
                        m_core->v__DOT__thecpu__DOT__gie,
                        m_core->v__DOT__thecpu__DOT__gie,
                        0,
                        0,
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
                        // m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
                        m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
 
 
                showins(ln, "Dc",
                showins(ln, "Dc",
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
 
 
                showins(ln, "Op",
                showins(ln, "Op",
                        m_core->v__DOT__thecpu__DOT__op_ce,
                        m_core->v__DOT__thecpu__DOT__op_ce,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
 
 
                showins(ln, "Al",
                showins(ln, "Al",
                        m_core->v__DOT__thecpu__DOT__alu_ce,
                        m_core->v__DOT__thecpu__DOT__alu_ce,
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                        m_core->v__DOT__thecpu__DOT__alu_gie,
                        m_core->v__DOT__thecpu__DOT__alu_gie,
                        m_core->v__DOT__thecpu__DOT__alu_stall,
                        m_core->v__DOT__thecpu__DOT__alu_stall,
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
        }
        }
        void    tick(void) {
        void    tick(void) {
                int gie = m_core->v__DOT__thecpu__DOT__gie;
                int gie = m_core->v__DOT__thecpu__DOT__gie;
                /*
                /*
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
                                                m_core->o_qspi_sck,
                                                m_core->o_qspi_sck,
                                                m_core->o_qspi_dat);
                                                m_core->o_qspi_dat);
                */
                */
 
 
                int stb = m_core->o_wb_stb;
                int stb = m_core->o_wb_stb;
                if ((m_core->o_wb_addr & (-1<<20))!=1)
                if ((m_core->o_wb_addr & (-1<<20))!=1)
                        stb = 0;
                        stb = 0;
                m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
                m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
                        m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
                        m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
                        m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
                        m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
                        m_core->i_wb_ack = 1;
                        m_core->i_wb_ack = 1;
 
 
                if ((dbg_flag)&&(dbg_fp)) {
                if ((dbg_flag)&&(dbg_fp)) {
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
                        fprintf(dbg_fp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
                                (m_core->i_dbg_cyc)?"CYC":"   ",
                                (m_core->i_dbg_cyc)?"CYC":"   ",
                                (m_core->i_dbg_stb)?"STB":
                                (m_core->i_dbg_stb)?"STB":
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
                                ((m_core->i_dbg_we)?"WE":"  "),
                                ((m_core->i_dbg_we)?"WE":"  "),
                                (m_core->i_dbg_addr),0,
                                (m_core->i_dbg_addr),0,
                                m_core->i_dbg_data,
                                m_core->i_dbg_data,
                                (m_core->o_dbg_ack)?"ACK":"   ",
                                (m_core->o_dbg_ack)?"ACK":"   ",
                                (m_core->o_dbg_stall)?"STALL":"     ",
                                (m_core->o_dbg_stall)?"STALL":"     ",
                                (m_core->o_dbg_data),
                                (m_core->o_dbg_data),
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
                                (m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
                                (m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
                                (m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
                                (m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
                                (m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
                        fprintf(dbg_fp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
                                (m_core->v__DOT__sys_we)?"WE":"  ",
                                (m_core->v__DOT__sys_we)?"WE":"  ",
                                (m_core->v__DOT__sys_addr),
                                (m_core->v__DOT__sys_addr),
                                (m_core->v__DOT__dbg_addr),
                                (m_core->v__DOT__dbg_addr),
                                (m_core->v__DOT__sys_data),
                                (m_core->v__DOT__sys_data),
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
                                (m_core->v__DOT__wb_data));
                                (m_core->v__DOT__wb_data));
                }
                }
 
 
                if (dbg_fp)
                if (dbg_fp)
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
                                m_core->v__DOT__thecpu__DOT__op_ce,
                                m_core->v__DOT__thecpu__DOT__op_ce,
                                m_core->v__DOT__thecpu__DOT__op_pc,
                                m_core->v__DOT__thecpu__DOT__op_pc,
                                m_core->v__DOT__thecpu__DOT__dcdA,
                                m_core->v__DOT__thecpu__DOT__dcdA,
                                m_core->v__DOT__thecpu__DOT__opR,
                                m_core->v__DOT__thecpu__DOT__opR,
                                m_core->v__DOT__cmd_halt,
                                m_core->v__DOT__cmd_halt,
                                m_core->v__DOT__cpu_halt,
                                m_core->v__DOT__cpu_halt,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__alu_wr,
                                m_core->v__DOT__thecpu__DOT__alu_wr,
                                m_core->v__DOT__thecpu__DOT__alu_reg,
                                m_core->v__DOT__thecpu__DOT__alu_reg,
                                m_core->v__DOT__thecpu__DOT__ipc,
                                m_core->v__DOT__thecpu__DOT__ipc,
                                m_core->v__DOT__thecpu__DOT__upc);
                                m_core->v__DOT__thecpu__DOT__upc);
 
 
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
                if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
                        fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
                                m_core->v__DOT__pic_interrupt,
                                m_core->v__DOT__pic_interrupt,
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
                                m_core->v__DOT__cmd_addr,
                                m_core->v__DOT__cmd_addr,
                                m_core->v__DOT__dbg_idata,
                                m_core->v__DOT__dbg_idata,
                                m_core->v__DOT__thecpu__DOT__master_ce,
                                m_core->v__DOT__thecpu__DOT__master_ce,
                                m_core->v__DOT__thecpu__DOT__alu_wr,
                                m_core->v__DOT__thecpu__DOT__alu_wr,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__mem_valid);
                                m_core->v__DOT__thecpu__DOT__mem_valid);
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
                } else if ((dbg_fp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
                        fprintf(dbg_fp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
                                m_core->v__DOT__thecpu__DOT__wr_reg_vl,
                                m_core->v__DOT__cmd_addr,
                                m_core->v__DOT__cmd_addr,
                                m_core->v__DOT__dbg_idata,
                                m_core->v__DOT__dbg_idata,
                                m_core->v__DOT__thecpu__DOT__master_ce,
                                m_core->v__DOT__thecpu__DOT__master_ce,
                                m_core->v__DOT__thecpu__DOT__alu_wr,
                                m_core->v__DOT__thecpu__DOT__alu_wr,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__alu_valid,
                                m_core->v__DOT__thecpu__DOT__mem_valid,
                                m_core->v__DOT__thecpu__DOT__mem_valid,
                                m_core->v__DOT__thecpu__DOT__w_iflags,
                                m_core->v__DOT__thecpu__DOT__w_iflags,
                                m_core->v__DOT__thecpu__DOT__w_uflags);
                                m_core->v__DOT__thecpu__DOT__w_uflags);
                        fprintf(dbg_fp, "\tbrk=%d,%d\n",
                        fprintf(dbg_fp, "\tbrk=%d,%d\n",
                                m_core->v__DOT__thecpu__DOT__break_en,
                                m_core->v__DOT__thecpu__DOT__break_en,
                                m_core->v__DOT__thecpu__DOT__op_break);
                                m_core->v__DOT__thecpu__DOT__op_break);
                }
                }
 
 
                TESTB<Vzipsystem>::tick();
                TESTB<Vzipsystem>::tick();
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
                if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
                        fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
                                (gie)?"User":"Supervisor",
                                (gie)?"User":"Supervisor",
                                (gie)?"Supervisor":"User",
                                (gie)?"Supervisor":"User",
                                m_core->v__DOT__thecpu__DOT__ipc,
                                m_core->v__DOT__thecpu__DOT__ipc,
                                m_core->v__DOT__thecpu__DOT__upc,
                                m_core->v__DOT__thecpu__DOT__upc,
                                m_core->v__DOT__thecpu__DOT__pf_pc);
                                m_core->v__DOT__thecpu__DOT__pf_pc);
                } if (dbg_fp) {
                } if (dbg_fp) {
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
                                m_core->v__DOT__thecpu__DOT__opvalid,
                                m_core->v__DOT__thecpu__DOT__opvalid,
                                m_core->v__DOT__thecpu__DOT__op_gie,
                                m_core->v__DOT__thecpu__DOT__op_gie,
                                m_core->v__DOT__thecpu__DOT__op_stall,
                                m_core->v__DOT__thecpu__DOT__op_stall,
                                m_core->v__DOT__thecpu__DOT__op_pc-1);
                                m_core->v__DOT__thecpu__DOT__op_pc-1);
                        dbgins("Al - ",
                        dbgins("Al - ",
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_gie,
                                m_core->v__DOT__thecpu__DOT__alu_gie,
                                m_core->v__DOT__thecpu__DOT__alu_stall,
                                m_core->v__DOT__thecpu__DOT__alu_stall,
                                m_core->v__DOT__thecpu__DOT__alu_pc-1);
                                m_core->v__DOT__thecpu__DOT__alu_pc-1);
 
 
                }
                }
 
 
                if (m_core->v__DOT__cpu_dbg_we) {
 
                        printf("WRITE-ENABLE!!\n");
 
                        bomb = true;
 
                }
 
        }
        }
 
 
        bool    test_success(void) {
        bool    test_success(void) {
                return ((!m_core->v__DOT__thecpu__DOT__gie)
                return ((!m_core->v__DOT__thecpu__DOT__gie)
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
        }
        }
 
 
        bool    test_failure(void) {
        bool    test_failure(void) {
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
                        &&(!m_core->v__DOT__thecpu__DOT__alu_gie)
 
                        &&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
                        &&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
                                == 0x2f0f7fff));
                                == 0x2f0f7fff));
        }
        }
 
 
        void    wb_write(unsigned a, unsigned int v) {
        void    wb_write(unsigned a, unsigned int v) {
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
                m_core->i_dbg_cyc = 1;
                m_core->i_dbg_cyc = 1;
                m_core->i_dbg_stb = 1;
                m_core->i_dbg_stb = 1;
                m_core->i_dbg_we  = 1;
                m_core->i_dbg_we  = 1;
                m_core->i_dbg_addr = a & 1;
                m_core->i_dbg_addr = a & 1;
                m_core->i_dbg_data = v;
                m_core->i_dbg_data = v;
 
 
                tick();
                tick();
                while(m_core->o_dbg_stall)
                while(m_core->o_dbg_stall)
                        tick();
                        tick();
 
 
                m_core->i_dbg_stb = 0;
                m_core->i_dbg_stb = 0;
                while(!m_core->o_dbg_ack)
                while(!m_core->o_dbg_ack)
                        tick();
                        tick();
 
 
                // Release the bus
                // Release the bus
                m_core->i_dbg_cyc = 0;
                m_core->i_dbg_cyc = 0;
                m_core->i_dbg_stb = 0;
                m_core->i_dbg_stb = 0;
                tick();
                tick();
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_write -- complete");
                mvprintw(0,40, "wb_write -- complete");
        }
        }
 
 
        unsigned long   wb_read(unsigned a) {
        unsigned long   wb_read(unsigned a) {
                unsigned int    v;
                unsigned int    v;
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_read(0x%08x)", a);
                mvprintw(0,40, "wb_read(0x%08x)", a);
                m_core->i_dbg_cyc = 1;
                m_core->i_dbg_cyc = 1;
                m_core->i_dbg_stb = 1;
                m_core->i_dbg_stb = 1;
                m_core->i_dbg_we  = 0;
                m_core->i_dbg_we  = 0;
                m_core->i_dbg_addr = a & 1;
                m_core->i_dbg_addr = a & 1;
 
 
                tick();
                tick();
                while(m_core->o_dbg_stall)
                while(m_core->o_dbg_stall)
                        tick();
                        tick();
 
 
                m_core->i_dbg_stb = 0;
                m_core->i_dbg_stb = 0;
                while(!m_core->o_dbg_ack)
                while(!m_core->o_dbg_ack)
                        tick();
                        tick();
                v = m_core->o_dbg_data;
                v = m_core->o_dbg_data;
 
 
                // Release the bus
                // Release the bus
                m_core->i_dbg_cyc = 0;
                m_core->i_dbg_cyc = 0;
                m_core->i_dbg_stb = 0;
                m_core->i_dbg_stb = 0;
                tick();
                tick();
 
 
                mvprintw(0,35, "%40s", "");
                mvprintw(0,35, "%40s", "");
                mvprintw(0,40, "wb_read = 0x%08x", v);
                mvprintw(0,40, "wb_read = 0x%08x", v);
 
 
                return v;
                return v;
        }
        }
 
 
};
};
 
 
 
void    usage(void) {
 
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
 
        printf("\n");
 
        printf("\tWhere testfile.out is an output file from the assembler.\n");
 
        printf("\t-a\tSets the testbench to run automatically without any\n");
 
        printf("\t\tuser interaction.\n");
 
        printf("\n");
 
        printf("\tUser Commands:\n");
 
        printf("\t\tWhen the test bench is run interactively, the following\n");
 
        printf("\t\tkey strokes are recognized:\n");
 
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
 
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
 
        printf("\t\t\tuser intervention.\n");
 
        printf("\t\t\'q\'\tQuit the simulation.\n");
 
        printf("\t\t\'r\'\tReset the processor.\n");
 
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
 
        printf("\t\t\tThis may consume more than one tick.\n");
 
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
 
}
 
 
int     main(int argc, char **argv) {
int     main(int argc, char **argv) {
        Verilated::commandArgs(argc, argv);
        Verilated::commandArgs(argc, argv);
        ZIPPY_TB        *tb = new ZIPPY_TB();
        ZIPPY_TB        *tb = new ZIPPY_TB();
        ZPARSER         zp;
        bool            autorun = false, exit_on_done = false;
 
 
        printf("uCC = %d\n", (int)zp.ZIP_uCC);
 
        printf("MOV CC,R0 = 0x%08x\n", zp.op_mov(0,zp.ZIP_uCC, zp.ZIP_R0));
 
                // = 0x200e8000
 
                // Op = 0x2
 
                // Result = 0x0, R0 (Supervisor/default)
 
                // Cond   = 0x0
 
                // BReg   = 0xe (CC)
 
                // BMap   = 1, BReg = uCC
 
                //
 
 
 
        initscr();
 
        raw();
 
        noecho();
 
        keypad(stdscr, true);
 
 
 
        // mem[0x00000] = 0xbe000010; // Halt instruction
        // mem[0x00000] = 0xbe000010; // Halt instruction
        unsigned int mptr = 0;
        unsigned int mptr = 0;
 
 
        if (argc <= 1) {
        if (argc <= 1) {
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); //  0: CLR R0
                usage();
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R0,zp.ZIP_R1); //  1: MOV R0,R1
                exit(-1);
        tb->m_mem[mptr++] = zp.op_mov(1,zp.ZIP_R0,zp.ZIP_R2); //  2: MOV $1+R0,R2
 
        tb->m_mem[mptr++] = zp.op_mov(2,zp.ZIP_R0,zp.ZIP_R3); //  3: MOV $2+R0,R3
 
        tb->m_mem[mptr++] = zp.op_mov(0x022, zp.ZIP_R0, zp.ZIP_R4); //  4: MOV $22h+R0,R4
 
        tb->m_mem[mptr++] = zp.op_mov(0x377, zp.ZIP_R0, zp.ZIP_uR5); //  5: MOV $377h+R0,uR5
 
        tb->m_mem[mptr++] = zp.op_noop(); //  6: NOOP
 
        tb->m_mem[mptr++] = zp.op_add(0,zp.ZIP_R2,zp.ZIP_R0); //  7: ADD R2,R0
 
        tb->m_mem[mptr++] = zp.op_add(32,zp.ZIP_R0); //  8: ADD $32,R0
 
        tb->m_mem[mptr++] = zp.op_add(-33,zp.ZIP_R0); //  9: ADD -$33,R0
 
        tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_Z, zp.ZIP_R0); //  A: NOT.Z R0
 
        tb->m_mem[mptr++] = zp.op_clrf(zp.ZIP_R0); //  B: CLRF R0
 
        tb->m_mem[mptr++] = zp.op_ldi(5,zp.ZIP_R1); //  C: LDI $5,R1
 
        tb->m_mem[mptr++] = zp.op_cmp(0,zp.ZIP_R0,zp.ZIP_R1); //  D: CMP R0,R1
 
        tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_LT, zp.ZIP_R0); //  E: NOT.LT R0
 
        tb->m_mem[mptr++] = zp.op_not(zp.ZIPC_GE, zp.ZIP_R1); //  F: NOT.GE R1
 
        tb->m_mem[mptr++] = zp.op_lod(-7,zp.ZIP_PC, zp.ZIP_R2); // 10: LOD $-7(PC),R2
 
        tb->m_mem[mptr++] = zp.op_ldihi(0xdead, zp.ZIP_R3); // 11: LODIHI $deadh,R3
 
        tb->m_mem[mptr++] = zp.op_ldilo(0xbeef, zp.ZIP_R3); // 12: LODILO $beefh,R3
 
 
 
        // Let's build a software test bench.
 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R12);//  0: CLR R12
 
        tb->m_mem[mptr++] = zp.op_ldihi(0xc000,zp.ZIP_R12);
 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R12,zp.ZIP_uR12);
 
        tb->m_mem[mptr++] = zp.op_mov(10,zp.ZIP_PC,zp.ZIP_uPC);
 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); // Clear R0, and disable ints
 
        tb->m_mem[mptr++] = zp.op_sto(zp.ZIP_R0,0,zp.ZIP_R12);
 
        tb->m_mem[mptr++] = zp.op_rtu(); //  7: RTU     // Switch to user mode
 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_uCC, zp.ZIP_R0); // Check result
 
        tb->m_mem[mptr++] = zp.op_tst(-256,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_bnz(1);
 
        tb->m_mem[mptr++] = zp.op_halt();// On SUCCESS
 
        tb->m_mem[mptr++] = zp.op_busy(); // On FAILURE
 
 
 
 
 
        // Now for a series of tests.  If the test fails, call the trap
 
        // interrupt with the test number that failed.  Upon completion,
 
        // call the trap with #0.
 
 
 
        // Now for a series of tests.  If the test fails, call the trap
 
        // interrupt with the test number that failed.  Upon completion,
 
        // call the trap with #0.
 
 
 
        // Test LDI to PC
 
        // Some data registers
 
        tb->m_mem[mptr] = mptr + 5 + 0x0100000; mptr++;
 
        tb->m_mem[mptr++] = zp.op_ldi(0x020,zp.ZIP_CC); //  LDI $GIE,CC
 
        tb->m_mem[mptr++] = zp.op_ldi(0x0200,zp.ZIP_R11); //  LDI $200h,R11
 
        tb->m_mem[mptr++] = zp.op_lod(-4,zp.ZIP_PC,zp.ZIP_PC); //  1: LOD $-3(PC),PC
 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R11); //  2: CLR R11
 
        tb->m_mem[mptr++] = zp.op_noop(); //  3: NOOP
 
        tb->m_mem[mptr++] = zp.op_cmp(0,zp.ZIP_R11); //  4: CMP $0,R11
 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z, 0, zp.ZIP_R11,zp.ZIP_R10); //  5: STO.Z R11,(R12)
 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z, 0, zp.ZIP_R11,zp.ZIP_CC); //  5: STO.Z R11,(R12)
 
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); //  6: ADD $1,R0
 
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); //  7: ADD $1,R0
 
 
 
        // Let's test whether overflow works
 
        tb->m_mem[mptr++] = zp.op_ldi(0x0300,zp.ZIP_R11); //  0: LDI $3,R11
 
        tb->m_mem[mptr++] = zp.op_ldi(-1,zp.ZIP_R0); //  1: LDI $-1,R0
 
        tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0); //  R0 // R0 = max int
 
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R0); //  Should set ovfl
 
        tb->m_mem[mptr++] = zp.op_bv(1); //  4: BV $1+PC
 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
 
        // Overflow set from subtraction
 
        tb->m_mem[mptr++] = zp.op_ldi(0x0400,zp.ZIP_R11); //  6: LDI $4,R11
 
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); //  7: LDI $1,R0
 
        tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0); //  8: ROL $31,R0
 
        tb->m_mem[mptr++] = zp.op_sub(1,zp.ZIP_R0); // Should set ovfl
 
        tb->m_mem[mptr++] = zp.op_bv(1); //  A: BV $1+PC
 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
 
        // Overflow set from LSR
 
        tb->m_mem[mptr++] = zp.op_ldi(0x0500,zp.ZIP_R11); //  C: LDI $5,R11
 
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_bv(1);
 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
 
        // Overflow set from LSL
 
        tb->m_mem[mptr++] = zp.op_ldi(0x0600,zp.ZIP_R11);
 
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_rol(30,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_bv(1);
 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
 
        // Overflow set from LSL, negative to positive
 
        tb->m_mem[mptr++] = zp.op_ldi(0x0700,zp.ZIP_R11);
 
        tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_bv(1); //  A: BV $1+PC
 
        tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
 
 
 
 
 
        // Test carry
 
        tb->m_mem[mptr++] = zp.op_ldi(0x01000, zp.ZIP_R11); //  0: LDI $16,R11
 
        tb->m_mem[mptr++] = zp.op_ldi(-1, zp.ZIP_R0); //  1: LDI $-1,R0
 
        tb->m_mem[mptr++] = zp.op_add(1, zp.ZIP_R0); //  2: ADD $1,R0
 
        tb->m_mem[mptr++] = zp.op_tst(2, zp.ZIP_CC); //  3: TST $2,CC // Is the carry set?
 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z,0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
 
        // and carry from subtraction
 
        tb->m_mem[mptr++] = zp.op_ldi(0x01100, zp.ZIP_R11); //  0: LDI $17,R11
 
        tb->m_mem[mptr++] = zp.op_sub(1, zp.ZIP_R0); //  1: SUB $1,R0
 
        tb->m_mem[mptr++] = zp.op_tst(2, zp.ZIP_CC); //  2: TST $2,CC // Is the carry set?
 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_Z,0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
 
 
 
 
 
 
 
        // Let's try a loop: for i=0; i<5; i++)
 
        //      We'll use R0=i, Immediates for 5
 
        tb->m_mem[mptr++] = zp.op_ldi(0x01200, zp.ZIP_R11); //  0: LDI $18,R11
 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); //  0: CLR R0
 
        tb->m_mem[mptr++] = zp.op_noop();
 
        tb->m_mem[mptr++] = zp.op_add(1, zp.ZIP_R0); //  2: R0 = R0 + 1
 
        tb->m_mem[mptr++] = zp.op_cmp(5, zp.ZIP_R0); //  3: CMP $5,R0
 
        tb->m_mem[mptr++] = zp.op_blt(-4); //  4: BLT PC-4
 
        //
 
        // Let's try a reverse loop.  Such loops are usually cheaper to
 
        // implement, and this one is no different: 2 loop instructions 
 
        // (minus setup instructions) vs 3 from before.
 
        // R0 = 5; (from before)
 
        // do {
 
        // } while (R0 > 0);
 
        tb->m_mem[mptr++] = zp.op_ldi(0x01300, zp.ZIP_R11); //  0: LDI $18,R11
 
        tb->m_mem[mptr++] = zp.op_noop(); //  5: NOOP
 
        tb->m_mem[mptr++] = zp.op_sub( 1, zp.ZIP_R0); //  6: R0 = R0 - 1
 
        tb->m_mem[mptr++] = zp.op_bgt(-3); //  7: BGT PC-3
 
        // How about the same thing with a >= comparison?
 
        // R1 = 5; // Need to do this explicitly
 
        // do {
 
        // } while(R1 >= 0);
 
        tb->m_mem[mptr++] = zp.op_ldi(0x01400, zp.ZIP_R11); //  0: LDI $18,R11
 
        tb->m_mem[mptr++] = zp.op_ldi(5, zp.ZIP_R1);
 
        tb->m_mem[mptr++] = zp.op_noop();
 
        tb->m_mem[mptr++] = zp.op_sub(1, zp.ZIP_R1);
 
        tb->m_mem[mptr++] = zp.op_bge(-3);
 
 
 
        // Let's try the reverse loop again, only this time we'll store our
 
        // loop variable in memory.
 
        // R0 = 5; (from before)
 
        // do {
 
        // } while (R0 > 0);
 
        tb->m_mem[mptr++] = zp.op_ldi(0x01500, zp.ZIP_R11); //  0: LDI $18,R11
 
        tb->m_mem[mptr++] = zp.op_bra(1); // Give us a memory location
 
        tb->m_mem[mptr++] = 5; // Loop five times
 
        tb->m_mem[mptr++] = zp.op_mov(-2, zp.ZIP_PC, zp.ZIP_R1); // Get var adr
 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R2);
 
        tb->m_mem[mptr++] = zp.op_ldi(5, zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_sto(zp.ZIP_R0,0,zp.ZIP_R1);
 
        tb->m_mem[mptr++] = zp.op_add(1,zp.ZIP_R2);
 
        tb->m_mem[mptr++] = zp.op_add(14,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_lod(0,zp.ZIP_R1,zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_sub( 1, zp.ZIP_R0);
 
        tb->m_mem[mptr++] = zp.op_bgt(-6);
 
        tb->m_mem[mptr++] = zp.op_cmp( 5, zp.ZIP_R2);
 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIPC_NZ, 0, zp.ZIP_R11, zp.ZIP_CC);
 
 
 
        // Return success / Test the trap interrupt
 
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R11); //  0: CLR R11
 
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R11, zp.ZIP_CC);
 
        tb->m_mem[mptr++] = zp.op_noop(); //  2: NOOP // Give it a chance to take
 
        tb->m_mem[mptr++] = zp.op_noop(); //  3: NOOP // effect
 
 
 
        // Go into an infinite loop if the trap fails
 
        // Permanent loop instruction -- a busy halt if you will
 
        tb->m_mem[mptr++] = zp.op_busy(); //  4: BRA PC-1
 
 
 
        // And, in case we miss a halt ...
 
        tb->m_mem[mptr++] = zp.op_halt(); // HALT
 
 
 
        } else {
        } else {
                for(int argn=1; argn<argc; argn++) {
                for(int argn=1; argn<argc; argn++) {
                        if (access(argv[argn], R_OK)==0) {
                        if (argv[argn][0] == '-') {
 
                                switch(argv[argn][1]) {
 
                                case 'a':
 
                                        autorun = true;
 
                                        break;
 
                                case 'e':
 
                                        exit_on_done = true;
 
                                        break;
 
                                case 'h':
 
                                        usage();
 
                                        exit(0);
 
                                        break;
 
                                default:
 
                                        usage();
 
                                        exit(-1);
 
                                        break;
 
                                }
 
                        } else if (access(argv[argn], R_OK)==0) {
                                FILE *fp = fopen(argv[argn], "r");
                                FILE *fp = fopen(argv[argn], "r");
                                if (fp == NULL) {
                                if (fp == NULL) {
                                        printf("Cannot open %s\n", argv[argn]);
                                        printf("Cannot open %s\n", argv[argn]);
                                        perror("O/S Err: ");
                                        perror("O/S Err: ");
                                        exit(-1);
                                        exit(-1);
                                } mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
                                } mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
                                fclose(fp);
                                fclose(fp);
                        }
                        }
                }
                }
        }
        }
 
 
 
        if (autorun) {
 
                bool    done = false;
 
 
 
                printf("Running in non-interactive mode\n");
 
                tb->reset();
 
                for(int i=0; i<2; i++)
 
                        tb->tick();
 
                tb->m_core->v__DOT__cmd_halt = 0;
 
                while(!done) {
 
                        tb->tick();
 
 
 
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
 
                                // tb->m_core->v__DOT__cmd_halt = 0;
 
                                // tb->m_core->v__DOT__cmd_step = 0;
 
 
 
                        printf("PC = %08x:%08x (%08x)\n",
 
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
 
                                tb->m_core->v__DOT__thecpu__DOT__upc,
 
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
 
 
 
                        done = (tb->test_success())||(tb->test_failure());
 
                }
 
        } else { // Interactive
 
                initscr();
 
                raw();
 
                noecho();
 
                keypad(stdscr, true);
 
 
        tb->reset();
        tb->reset();
 
                for(int i=0; i<2; i++)
 
                        tb->tick();
 
                tb->m_core->v__DOT__cmd_halt = 0;
 
 
        int     chv = 'q';
        int     chv = 'q';
        const   bool    live_debug_mode = true;
 
 
 
        if (live_debug_mode) {
 
                bool    done = false, halted = true, manual = true;
                bool    done = false, halted = true, manual = true;
 
 
                halfdelay(1);
                halfdelay(1);
                tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
                        // tb->show_state();
                        // tb->show_state();
 
 
                while(!done) {
                while(!done) {
                        chv = getch();
                        chv = getch();
                        switch(chv) {
                        switch(chv) {
                        case 'h': case 'H':
                        case 'h': case 'H':
                                tb->wb_write(CMD_REG, CMD_HALT);
                                tb->wb_write(CMD_REG, CMD_HALT);
                                if (!halted)
                                if (!halted)
                                        erase();
                                        erase();
                                halted = true;
                                halted = true;
                                break;
                                break;
                        case 'g': case 'G':
                        case 'g': case 'G':
                                tb->wb_write(CMD_REG, 0);
                                tb->wb_write(CMD_REG, 0);
                                if (halted)
                                if (halted)
                                        erase();
                                        erase();
                                halted = false;
                                halted = false;
                                manual = false;
                                manual = false;
                                break;
                                break;
                        case 'q': case 'Q':
                        case 'q': case 'Q':
                                done = true;
                                done = true;
                                break;
                                break;
                        case 'r': case 'R':
                        case 'r': case 'R':
                                tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
                                tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
                                halted = true;
                                halted = true;
                                erase();
                                erase();
                                break;
                                break;
                        case 's': case 'S':
                        case 's': case 'S':
 
                                if (manual)
 
                                        erase();
                                tb->wb_write(CMD_REG, CMD_STEP);
                                tb->wb_write(CMD_REG, CMD_STEP);
                                manual = false;
                                manual = false;
                                break;
                                break;
                        case 't': case 'T':
                        case 't': case 'T':
 
                                if (!manual)
 
                                        erase();
                                manual = true;
                                manual = true;
 
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
 
                //              tb->m_core->v__DOT__cmd_halt = 0;
 
                //              tb->m_core->v__DOT__cmd_step = 0;
                                tb->tick();
                                tb->tick();
                                break;
                                break;
                        case ERR:
                        case ERR:
                        default:
                        default:
                                if (!manual)
                                if (!manual)
                                        tb->tick();
                                        tb->tick();
                        }
                        }
 
 
                        if (manual) {
                        if (manual) {
                                tb->show_state();
                                tb->show_state();
                        } else if (halted) {
                        } else if (halted) {
                                if (tb->dbg_fp)
                                if (tb->dbg_fp)
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
                                        fprintf(tb->dbg_fp, "\n\nREAD-STATE ******\n");
                                tb->read_state();
                                tb->read_state();
                        } else
                        } else
                                tb->show_state();
                                tb->show_state();
 
 
                        if (tb->m_core->i_rst)
                        if (tb->m_core->i_rst)
                                done =true;
                                done =true;
                        if (tb->bomb)
                        if (tb->bomb)
                                done = true;
                                done = true;
                }
 
 
 
        } else { // Manual stepping mode
                        if (exit_on_done) {
 
                                if (tb->test_success())
 
                                        done = true;
 
                                if (tb->test_failure())
 
                                        done = true;
 
                        }
 
                }
 
                endwin();
 
        }
 
#ifdef  MANUAL_STEPPING_MODE
 
         else { // Manual stepping mode
                tb->show_state();
                tb->show_state();
 
 
                while('q' != tolower(chv = getch())) {
                while('q' != tolower(chv = getch())) {
                        tb->tick();
                        tb->tick();
                        tb->show_state();
                        tb->show_state();
 
 
                        if (tb->test_success())
                        if (tb->test_success())
                                break;
                                break;
                        else if (tb->test_failure())
                        else if (tb->test_failure())
                                break;
                                break;
                }
                }
        }
        }
 
#endif
 
 
        endwin();
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
 
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
 
        if (tb->m_core->v__DOT__mtc_data != 0)
 
                printf("Instructions / Clock: %.2f\n",
 
                        (double)tb->m_core->v__DOT__mic_data
 
                        / (double)tb->m_core->v__DOT__mtc_data);
        if (tb->test_success())
        if (tb->test_success())
                printf("SUCCESS!\n");
                printf("SUCCESS!\n");
        else if (tb->test_failure())
        else if (tb->test_failure())
                printf("TEST FAILED!\n");
                printf("TEST FAILED!\n");
        else if (chv == 'q')
        else
                printf("chv = %c\n", chv);
                printf("User quit\n");
        exit(0);
        exit(0);
}
}
 
 
 
 

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