OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Diff between revs 36 and 39

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Rev 36 Rev 39
Line 41... Line 41...
#include <ctype.h>
#include <ctype.h>
#include <ncurses.h>
#include <ncurses.h>
 
 
#include "verilated.h"
#include "verilated.h"
#include "Vzipsystem.h"
#include "Vzipsystem.h"
 
#include "cpudefs.h"
 
 
#include "testb.h"
#include "testb.h"
// #include "twoc.h"
// #include "twoc.h"
// #include "qspiflashsim.h"
// #include "qspiflashsim.h"
#include "memsim.h"
#include "memsim.h"
Line 182... Line 183...
 
 
        void    show_state(void) {
        void    show_state(void) {
                int     ln= 0;
                int     ln= 0;
 
 
                mvprintw(ln,0, "Peripherals-SS"); ln++;
                mvprintw(ln,0, "Peripherals-SS"); ln++;
 
#ifdef  OPT_ILLEGAL_INSTRUCTION
                printw(" %s",
                printw(" %s",
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
                        );
                        );
                /*
#endif
                printw(" %s%s%s",
 
                        (m_core->v__DOT__thecpu__DOT__ill_err)?"IL":"  ",
#ifdef  OPT_EARLY_BRANCHING
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":"  ",
                printw(" %s%s",
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":"  ",
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
                        (m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ");
                        );
#endif
                */
 
 
 
                /*
                /*
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
                showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
                        mvprintw(ln, 17, "%s%s",
                        mvprintw(ln, 17, "%s%s",
                                ((m_core->v__DOT__sys_cyc)
                                ((m_core->v__DOT__sys_cyc)
Line 303... Line 304...
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
                showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
 
 
                attroff(A_BOLD);
                attroff(A_BOLD);
                ln+=1;
                ln+=1;
 
 
 
#ifdef  OPT_SINGLE_FETCH
 
        ln+=2;
 
#else
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
                mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
                        m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
Line 323... Line 327...
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
                        (m_core->v__DOT__thecpu__DOT__pf_addr),
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
                        (m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
                        (m_core->v__DOT__wb_data)); ln++;
                        (m_core->v__DOT__wb_data)); ln++;
 
#endif
 
 
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
                        (m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
                                :((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":"   "),
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
Line 334... Line 339...
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
                        (m_core->v__DOT__thecpu__DOT__mem_addr),
                        (m_core->v__DOT__thecpu__DOT__mem_data),
                        (m_core->v__DOT__thecpu__DOT__mem_data),
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
                        (m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
                        (m_core->v__DOT__thecpu__DOT__mem_result));
 
// #define      OPT_PIPELINED_BUS_ACCESS
 
#ifdef  OPT_PIPELINED_BUS_ACCESS
 
                printw(" %x%x%c%c",
 
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
 
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
 
                        (m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-',
 
                        (mem_pipe_stalled())?'S':'-'); ln++;
 
#else
 
                ln++;
 
#endif
 
 
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
                        (m_core->o_wb_cyc)?"CYC":"   ",
                        (m_core->o_wb_cyc)?"CYC":"   ",
                        (m_core->o_wb_stb)?"STB":"   ",
                        (m_core->o_wb_stb)?"STB":"   ",
Line 346... Line 361...
                        (m_core->o_wb_addr),
                        (m_core->o_wb_addr),
                        (m_core->o_wb_data),
                        (m_core->o_wb_data),
                        (m_core->i_wb_ack)?"ACK":"   ",
                        (m_core->i_wb_ack)?"ACK":"   ",
                        (m_core->i_wb_stall)?"STL":"   ",
                        (m_core->i_wb_stall)?"STL":"   ",
                        (m_core->i_wb_data)); ln+=2;
                        (m_core->i_wb_data)); ln+=2;
 
#ifdef  OPT_PIPELINED_BUS_ACCESS
 
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
 
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
 
                        (m_core->v__DOT__thecpu__DOT__master_ce),
 
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
 
                        (!m_core->v__DOT__thecpu__DOT__clear_pipeline),
 
                        (m_core->v__DOT__thecpu__DOT__set_cond),
 
                        (!m_core->v__DOT__thecpu__DOT__mem_stalled),
 
 
 
                        (m_core->v__DOT__thecpu__DOT__mem_stalled),
 
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
 
                        (m_core->v__DOT__thecpu__DOT__master_ce),
 
                        (mem_pipe_stalled()),
 
                        (!m_core->v__DOT__thecpu__DOT__op_pipe),
 
                        (m_core->v__DOT__thecpu__DOT__mem_busy));
 
                printw(" op_pipe = %d%d%d%d%d(%d|%d)",
 
                        (m_core->v__DOT__thecpu__DOT__dcdvalid),
 
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem),
 
                        (m_core->v__DOT__thecpu__DOT__dcdM),
 
                        (!((m_core->v__DOT__thecpu__DOT__dcdOp
 
                                ^m_core->v__DOT__thecpu__DOT__opn)&1)),
 
                        (m_core->v__DOT__thecpu__DOT__dcdB
 
                                == m_core->v__DOT__thecpu__DOT__op_B),
 
                        (m_core->v__DOT__thecpu__DOT__r_dcdI
 
                                == m_core->v__DOT__thecpu__DOT__r_opI),
 
                        (m_core->v__DOT__thecpu__DOT__r_dcdI+1
 
                                == m_core->v__DOT__thecpu__DOT__r_opI));
 
                mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
 
                        (m_core->v__DOT__thecpu__DOT__r_dcdI),
 
                        (m_core->v__DOT__thecpu__DOT__r_opI));
 
#endif
 
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
 
 
 
 
                showins(ln, "I ",
                showins(ln, "I ",
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__pf_valid,
                        m_core->v__DOT__thecpu__DOT__pf_valid,
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
Line 362... Line 410...
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
                        m_core->v__DOT__thecpu__DOT__dcd_ce,
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
                        m_core->v__DOT__thecpu__DOT__dcdvalid,
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
 
#ifdef  OPT_ILLEGAL_INSTRUCTION
 
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
 
                        mvprintw(ln-1,10,"I");
 
                else
 
#endif
 
                if (m_core->v__DOT__thecpu__DOT__dcdM)
 
                        mvprintw(ln-1,10,"M");
 
 
                showins(ln, "Op",
                showins(ln, "Op",
                        m_core->v__DOT__thecpu__DOT__op_ce,
                        m_core->v__DOT__thecpu__DOT__op_ce,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
                        op_pc()); ln++;
 
#ifdef  OPT_ILLEGAL_INSTRUCTION
 
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
 
                        mvprintw(ln-1,10,"I");
 
                else
 
#endif
 
                if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
 
                        mvprintw(ln-1,10,"M");
 
                else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
 
                        mvprintw(ln-1,10,"A");
 
 
                showins(ln, "Al",
                showins(ln, "Al",
                        m_core->v__DOT__thecpu__DOT__alu_ce,
                        m_core->v__DOT__thecpu__DOT__alu_ce,
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                        m_core->v__DOT__thecpu__DOT__alu_gie,
                        m_core->v__DOT__thecpu__DOT__alu_gie,
                        m_core->v__DOT__thecpu__DOT__alu_stall,
                        m_core->v__DOT__thecpu__DOT__alu_stall,
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
                        alu_pc()); ln++;
 
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
 
                        mvprintw(ln-1,10,"W");
 
 
                mvprintw(ln-5, 48,"%s %s",
                mvprintw(ln-5, 65,"%s %s",
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
                        (m_core->v__DOT__thecpu__DOT__op_break)?"OB":"  ",
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
                        (m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":"    ");
                mvprintw(ln-4, 48,
                mvprintw(ln-4, 48,
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
                printw("(%s:%02x,%x)",
                printw("(%s:%02x,%x)",
Line 413... Line 479...
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
                mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
                        (m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
                        (m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":"    ",
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":"    ",
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
                        zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
        }
        }
 
 
        unsigned int    cmd_read(unsigned int a) {
        unsigned int    cmd_read(unsigned int a) {
                if (dbg_fp) {
                if (dbg_fp) {
Line 597... Line 663...
                showins(ln, "Op",
                showins(ln, "Op",
                        m_core->v__DOT__thecpu__DOT__op_ce,
                        m_core->v__DOT__thecpu__DOT__op_ce,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__opvalid,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__op_gie,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_stall,
                        m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
                        op_pc()); ln++;
 
 
                showins(ln, "Al",
                showins(ln, "Al",
                        m_core->v__DOT__thecpu__DOT__alu_ce,
                        m_core->v__DOT__thecpu__DOT__alu_ce,
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                        m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                        m_core->v__DOT__thecpu__DOT__alu_gie,
                        m_core->v__DOT__thecpu__DOT__alu_gie,
                        m_core->v__DOT__thecpu__DOT__alu_stall,
                        m_core->v__DOT__thecpu__DOT__alu_stall,
                        m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
                        alu_pc()); ln++;
        }
        }
        void    tick(void) {
        void    tick(void) {
                int gie = m_core->v__DOT__thecpu__DOT__gie;
                int gie = m_core->v__DOT__thecpu__DOT__gie;
                /*
                /*
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
Line 658... Line 724...
                if (dbg_fp)
                if (dbg_fp)
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
                        fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
                                m_core->v__DOT__thecpu__DOT__dcd_ce,
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
                                m_core->v__DOT__thecpu__DOT__op_ce,
                                m_core->v__DOT__thecpu__DOT__op_ce,
                                m_core->v__DOT__thecpu__DOT__op_pc,
                                op_pc(),
                                m_core->v__DOT__thecpu__DOT__dcdA,
                                m_core->v__DOT__thecpu__DOT__dcdA,
                                m_core->v__DOT__thecpu__DOT__opR,
                                m_core->v__DOT__thecpu__DOT__opR,
                                m_core->v__DOT__cmd_halt,
                                m_core->v__DOT__cmd_halt,
                                m_core->v__DOT__cpu_halt,
                                m_core->v__DOT__cpu_halt,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
Line 749... Line 815...
                } if (dbg_fp) {
                } if (dbg_fp) {
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
                        dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
                                m_core->v__DOT__thecpu__DOT__opvalid,
                                m_core->v__DOT__thecpu__DOT__opvalid,
                                m_core->v__DOT__thecpu__DOT__op_gie,
                                m_core->v__DOT__thecpu__DOT__op_gie,
                                m_core->v__DOT__thecpu__DOT__op_stall,
                                m_core->v__DOT__thecpu__DOT__op_stall,
                                m_core->v__DOT__thecpu__DOT__op_pc-1);
                                op_pc());
                        dbgins("Al - ",
                        dbgins("Al - ",
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_ce,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
                                m_core->v__DOT__thecpu__DOT__alu_gie,
                                m_core->v__DOT__thecpu__DOT__alu_gie,
                                m_core->v__DOT__thecpu__DOT__alu_stall,
                                m_core->v__DOT__thecpu__DOT__alu_stall,
                                m_core->v__DOT__thecpu__DOT__alu_pc-1);
                                alu_pc());
 
 
                }
                }
        }
        }
 
 
        bool    test_success(void) {
        bool    test_success(void) {
                return ((!m_core->v__DOT__thecpu__DOT__gie)
                return ((!m_core->v__DOT__thecpu__DOT__gie)
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
        }
        }
 
 
 
        unsigned        op_pc(void) {
 
                /*
 
                unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
 
                if (m_core->v__DOT__thecpu__DOT__dcdvalid)
 
                        r--;
 
                return r;
 
                */
 
                return m_core->v__DOT__thecpu__DOT__op_pc-1;
 
        }
 
 
 
        unsigned        alu_pc(void) {
 
                /*
 
                unsigned        r = op_pc();
 
                if (m_core->v__DOT__thecpu__DOT__opvalid)
 
                        r--;
 
                return r;
 
                */
 
                return m_core->v__DOT__thecpu__DOT__alu_pc-1;
 
        }
 
 
 
#ifdef  OPT_PIPELINED_BUS_ACCESS
 
        int     mem_pipe_stalled(void) {
 
                int     r = 0;
 
                r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
 
                 ||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
 
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
 
                        ||(
 
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
 
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
 
                return r;
 
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
 
        }
 
#endif
 
 
        bool    test_failure(void) {
        bool    test_failure(void) {
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
                        &&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
                                == 0x2f0f7fff)
 
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
        }
        }
 
 
        void    wb_write(unsigned a, unsigned int v) {
        void    wb_write(unsigned a, unsigned int v) {
                int     errcount = 0;
                int     errcount = 0;
Line 1115... Line 1214...
                                else
                                else
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
                                halted = true;
                                halted = true;
                                erase();
                                erase();
                                break;
                                break;
                        case 's': case 'S':
                        case 's':
                                if (!halted)
                                if (!halted)
                                        erase();
                                        erase();
                                tb->wb_write(CMD_REG, CMD_STEP);
                                tb->wb_write(CMD_REG, CMD_STEP);
                                manual = false;
                                manual = false;
                                halted = true;
                                halted = true;
                                break;
                                break;
                        case 't': case 'T':
                        case 'S':
 
                                if ((!manual)||(halted))
 
                                        erase();
 
                                manual = true;
 
                                halted = true;
 
                                tb->m_core->v__DOT__cmd_halt = 0;
 
                                tb->m_core->v__DOT__cmd_step = 1;
 
                                tb->eval();
 
                                tb->tick();
 
                                break;
 
                        case 'T': // 
 
                                if ((!manual)||(halted))
 
                                        erase();
 
                                manual = true;
 
                                halted = true;
 
                                tb->m_core->v__DOT__cmd_halt = 1;
 
                                tb->m_core->v__DOT__cmd_step = 0;
 
                                tb->eval();
 
                                tb->tick();
 
                                break;
 
                        case 't':
                                if ((!manual)||(halted))
                                if ((!manual)||(halted))
                                        erase();
                                        erase();
                                manual = true;
                                manual = true;
                                halted = false;
                                halted = false;
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;

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