Line 63... |
Line 63... |
|
|
#define KEY_ESCAPE 27
|
#define KEY_ESCAPE 27
|
#define KEY_RETURN 10
|
#define KEY_RETURN 10
|
#define CTRL(X) ((X)&0x01f)
|
#define CTRL(X) ((X)&0x01f)
|
|
|
|
#define MAXERR 10000
|
|
|
// No particular "parameters" need definition or redefinition here.
|
// No particular "parameters" need definition or redefinition here.
|
class ZIPPY_TB : public TESTB<Vzipsystem> {
|
class ZIPPY_TB : public TESTB<Vzipsystem> {
|
public:
|
public:
|
unsigned long m_mem_size;
|
unsigned long m_mem_size;
|
MEMSIM m_mem;
|
MEMSIM m_mem;
|
Line 209... |
Line 211... |
(m_core->v__DOT__trap_int)?"I":" ");
|
(m_core->v__DOT__trap_int)?"I":" ");
|
*/
|
*/
|
showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
|
showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
|
showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
|
showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
|
// showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
|
// showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
|
|
|
|
if (!m_show_user_timers) {
|
|
showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
|
|
} else {
|
|
showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
|
|
}
|
|
|
showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
|
showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
|
|
|
ln++;
|
ln++;
|
showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
|
showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
|
showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
|
showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
|
Line 236... |
Line 245... |
|
|
ln++;
|
ln++;
|
mvprintw(ln, 40, "%s %s",
|
mvprintw(ln, 40, "%s %s",
|
(m_core->v__DOT__cpu_halt)? "CPU-HALT": " ",
|
(m_core->v__DOT__cpu_halt)? "CPU-HALT": " ",
|
(m_core->v__DOT__cpu_reset)?"CPU-RESET":" "); ln++;
|
(m_core->v__DOT__cpu_reset)?"CPU-RESET":" "); ln++;
|
mvprintw(ln, 40, "%s %s %s 0x%02x",
|
mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
|
(m_core->v__DOT__cmd_halt)? "HALT": " ",
|
(m_core->v__DOT__cmd_halt)? "HALT": " ",
|
(m_core->v__DOT__cmd_reset)?"RESET":" ",
|
(m_core->v__DOT__cmd_reset)?"RESET":" ",
|
(m_core->v__DOT__cmd_step)? "STEP" :" ",
|
(m_core->v__DOT__cmd_step)? "STEP" :" ",
|
(m_core->v__DOT__cmd_addr)&0x3f);
|
(m_core->v__DOT__cmd_addr)&0x3f,
|
|
(m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
|
|
(m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
|
if (m_core->v__DOT__thecpu__DOT__gie)
|
if (m_core->v__DOT__thecpu__DOT__gie)
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
else
|
else
|
attron(A_BOLD);
|
attron(A_BOLD);
|
mvprintw(ln, 0, "Supervisor Registers");
|
mvprintw(ln, 0, "Supervisor Registers");
|
Line 387... |
Line 398... |
(m_core->v__DOT__thecpu__DOT__mem_stalled),
|
(m_core->v__DOT__thecpu__DOT__mem_stalled),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__master_ce),
|
(m_core->v__DOT__thecpu__DOT__master_ce),
|
(mem_pipe_stalled()),
|
(mem_pipe_stalled()),
|
(!m_core->v__DOT__thecpu__DOT__op_pipe),
|
(!m_core->v__DOT__thecpu__DOT__op_pipe),
|
(m_core->v__DOT__thecpu__DOT__mem_busy));
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
|
(m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
|
|
#else
|
|
(m_core->v__DOT__thecpu__DOT__mem_busy)
|
|
#endif
|
|
);
|
printw(" op_pipe = %d%d%d%d%d(%d|%d)",
|
printw(" op_pipe = %d%d%d%d%d(%d|%d)",
|
(m_core->v__DOT__thecpu__DOT__dcdvalid),
|
(m_core->v__DOT__thecpu__DOT__dcdvalid),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__dcdM),
|
(m_core->v__DOT__thecpu__DOT__dcdM),
|
(!((m_core->v__DOT__thecpu__DOT__dcdOp
|
(!((m_core->v__DOT__thecpu__DOT__dcdOp
|
Line 405... |
Line 421... |
mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
|
mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
|
(m_core->v__DOT__thecpu__DOT__r_dcdI),
|
(m_core->v__DOT__thecpu__DOT__r_dcdI),
|
(m_core->v__DOT__thecpu__DOT__r_opI));
|
(m_core->v__DOT__thecpu__DOT__r_opI));
|
#endif
|
#endif
|
mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
|
mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
|
printw(" A:%c%c B:%c",
|
#ifdef OPT_SINGLE_CYCLE
|
|
printw(" A:%c%c B:%c%c",
|
(m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
|
(m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
|
(m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
|
(m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
|
(m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-');
|
(m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
|
|
(m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
|
|
#endif
|
|
|
|
|
showins(ln, "I ",
|
showins(ln, "I ",
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
Line 458... |
Line 477... |
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
alu_pc()); ln++;
|
alu_pc()); ln++;
|
if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
|
if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
|
mvprintw(ln-1,10,"W");
|
mvprintw(ln-1,10,"W");
|
|
else if (m_core->v__DOT__thecpu__DOT__alu_valid)
|
|
mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
|
|
else if (m_core->v__DOT__thecpu__DOT__mem_valid)
|
|
mvprintw(ln-1,10,"v");
|
|
else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
|
|
mvprintw(ln-1,10,"I");
|
|
// else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
|
|
// mvprintw(ln-1,10,"i");
|
|
|
mvprintw(ln-5, 65,"%s %s",
|
mvprintw(ln-5, 65,"%s %s",
|
(m_core->v__DOT__thecpu__DOT__op_break)?"OB":" ",
|
(m_core->v__DOT__thecpu__DOT__op_break)?"OB":" ",
|
(m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":" ");
|
(m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":" ");
|
mvprintw(ln-4, 48,
|
mvprintw(ln-4, 48,
|
Line 504... |
Line 531... |
void show_user_timers(bool v) {
|
void show_user_timers(bool v) {
|
m_show_user_timers = v;
|
m_show_user_timers = v;
|
}
|
}
|
|
|
unsigned int cmd_read(unsigned int a) {
|
unsigned int cmd_read(unsigned int a) {
|
|
int errcount = 0;
|
if (dbg_fp) {
|
if (dbg_fp) {
|
dbg_flag= true;
|
dbg_flag= true;
|
fprintf(dbg_fp, "CMD-READ(%d)\n", a);
|
fprintf(dbg_fp, "CMD-READ(%d)\n", a);
|
}
|
}
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
while((wb_read(CMD_REG) & CMD_STALL) == 0)
|
while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
|
;
|
errcount++;
|
|
if (errcount >= MAXERR) {
|
|
endwin();
|
|
|
|
printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
|
|
printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
|
|
printf("cpu-dbg-stall = %d\n", m_core->v__DOT__cpu_dbg_stall);
|
|
printf("pf_cyc = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
|
|
printf("mem_cyc_gbl = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
|
|
printf("mem_cyc_lcl = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
|
|
printf("opvalid = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
|
|
printf("dcdvalid = %d\n", m_core->v__DOT__thecpu__DOT__dcdvalid);
|
|
printf("dcd_ce = %d\n", m_core->v__DOT__thecpu__DOT__dcd_ce);
|
|
printf("dcd_stalled = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
|
|
printf("pf_valid = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
|
|
printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch);
|
|
printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb);
|
|
|
|
exit(-2);
|
|
}
|
|
|
|
assert(errcount < MAXERR);
|
unsigned int v = wb_read(CMD_DATA);
|
unsigned int v = wb_read(CMD_DATA);
|
|
|
if (dbg_flag)
|
if (dbg_flag)
|
fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
|
fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
|
v);
|
v);
|
dbg_flag = false;
|
dbg_flag = false;
|
return v;
|
return v;
|
}
|
}
|
|
|
void cmd_write(unsigned int a, int v) {
|
void cmd_write(unsigned int a, int v) {
|
|
int errcount = 0;
|
if ((a&0x0f)==0x0f)
|
if ((a&0x0f)==0x0f)
|
dbg_flag = true;
|
dbg_flag = true;
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
while((wb_read(CMD_REG) & CMD_STALL) == 0)
|
while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
|
;
|
errcount++;
|
|
assert(errcount < MAXERR);
|
if (dbg_flag)
|
if (dbg_flag)
|
fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
|
fprintf(dbg_fp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
|
wb_write(CMD_DATA, v);
|
wb_write(CMD_DATA, v);
|
}
|
}
|
|
|
Line 564... |
Line 615... |
if (v & 0x000080)
|
if (v & 0x000080)
|
printw("PIC Enabled ");
|
printw("PIC Enabled ");
|
} ln++;
|
} ln++;
|
showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
|
showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
|
showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
|
showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
|
// showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2));
|
showval(ln,40, "WBUS", cmd_read(32+ 2), false);
|
showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
|
showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
|
ln++;
|
ln++;
|
showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
|
showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
|
showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
|
showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
|
showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
|
showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
|
Line 675... |
Line 726... |
showins(ln, "I ",
|
showins(ln, "I ",
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
m_core->v__DOT__thecpu__DOT__gie,
|
m_core->v__DOT__thecpu__DOT__gie,
|
0,
|
0,
|
// m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
|
|
showins(ln, "Dc",
|
showins(ln, "Dc",
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
Line 843... |
Line 894... |
(gie)?"Supervisor":"User",
|
(gie)?"Supervisor":"User",
|
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__upc,
|
m_core->v__DOT__thecpu__DOT__upc,
|
m_core->v__DOT__thecpu__DOT__pf_pc);
|
m_core->v__DOT__thecpu__DOT__pf_pc);
|
} if (dbg_fp) {
|
} if (dbg_fp) {
|
|
dbgins("Dc - ", m_core->v__DOT__thecpu__DOT__dcd_ce,
|
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1);
|
dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
|
dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
op_pc());
|
op_pc());
|
|
/*
|
|
#ifdef OPT_SINGLE_CYCLE
|
|
fprintf(dbg_fp, "\t\t A = %08x, B = %08x, I = %08x, B+I = %08x, %c%c %s%s%s[%2x] = %08x %s\n",
|
|
m_core->v__DOT__thecpu__DOT__r_opA,
|
|
m_core->v__DOT__thecpu__DOT__r_opB,
|
|
m_core->v__DOT__thecpu__DOT__w_opBnI,
|
|
m_core->v__DOT__thecpu__DOT__r_dcdI,
|
|
(m_core->v__DOT__thecpu__DOT__opvalid_alu)?'A':'-',
|
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem)?'M':'-',
|
|
(m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"W":" ",
|
|
(m_core->v__DOT__thecpu__DOT__alu_wr)?"A":"M",
|
|
(m_core->v__DOT__thecpu__DOT__alu_ce)?"k":"-",
|
|
(m_core->v__DOT__thecpu__DOT__wr_reg_id),
|
|
(m_core->v__DOT__thecpu__DOT__wr_reg_vl),
|
|
(m_core->v__DOT__thecpu__DOT__mem_rdbusy)?"Mem-RdBusy":
|
|
((m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)?"Mem-Busy":""));
|
|
fprintf(dbg_fp, "\t\topA = %08x, opB = %08x, alu_result = %08x\n",
|
|
m_core->v__DOT__thecpu__DOT__opA,
|
|
m_core->v__DOT__thecpu__DOT__opB,
|
|
m_core->v__DOT__thecpu__DOT__alu_result);
|
|
#endif
|
|
*/
|
dbgins("Al - ",
|
dbgins("Al - ",
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|