| Line 9... |
Line 9... |
// code to load into memory. For now, we hand assemble with the
|
// code to load into memory. For now, we hand assemble with the
|
// computers help.
|
// computers help.
|
//
|
//
|
//
|
//
|
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Tecnology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
// Copyright (C) 2015, Gisselquist Technology, LLC
|
//
|
//
|
| Line 77... |
Line 77... |
bool dbg_flag, bomb, m_show_user_timers;
|
bool dbg_flag, bomb, m_show_user_timers;
|
int m_cursor;
|
int m_cursor;
|
unsigned long m_last_instruction_tickcount;
|
unsigned long m_last_instruction_tickcount;
|
|
|
ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
|
ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
|
if (false) {
|
if (true) {
|
dbg_fp = fopen("dbg.txt", "w");
|
dbg_fp = fopen("dbg.txt", "w");
|
dbg_flag = true;
|
dbg_flag = true;
|
} else {
|
} else {
|
dbg_fp = NULL;
|
dbg_fp = NULL;
|
dbg_flag = false;
|
dbg_flag = false;
|
| Line 96... |
Line 96... |
} else {
|
} else {
|
m_profile_fp = NULL;
|
m_profile_fp = NULL;
|
}
|
}
|
}
|
}
|
|
|
|
~ZIPPY_TB(void) {
|
|
if (dbg_fp)
|
|
fclose(dbg_fp);
|
|
if (m_profile_fp)
|
|
fclose(m_profile_fp);
|
|
}
|
|
|
void reset(void) {
|
void reset(void) {
|
// m_flash.debug(false);
|
// m_flash.debug(false);
|
TESTB<Vzipsystem>::reset();
|
TESTB<Vzipsystem>::reset();
|
}
|
}
|
|
|
| Line 127... |
Line 134... |
// 4,4,8,1 = 17 of 20, +3 = 19
|
// 4,4,8,1 = 17 of 20, +3 = 19
|
if (c)
|
if (c)
|
mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
|
mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
|
else
|
else
|
mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
|
mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
|
addch( ((r == m_core->v__DOT__thecpu__DOT__dcdA)
|
#ifdef OPT_PIPELINED
|
&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
|
addch( ((r == (int)(dcdA()&0x01f))
|
|
&&(dcdvalid())
|
&&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
|
&&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
|
?'a':((c)?'<':' '));
|
?'a':((c)?'<':' '));
|
addch( ((r == m_core->v__DOT__thecpu__DOT__dcdB)
|
addch( ((r == (int)(dcdB()&0x01f))
|
&&(m_core->v__DOT__thecpu__DOT__dcdvalid)
|
&&(dcdvalid())
|
&&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
|
&&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
|
?'b':((c)?'<':' '));
|
?'b':((c)?'<':' '));
|
|
#endif
|
addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
|
addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
|
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
|
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
|
?'W':((c)?'<':' '));
|
?'W':((c)?'<':' '));
|
}
|
}
|
|
|
| Line 203... |
Line 212... |
(m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":" "
|
(m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":" "
|
);
|
);
|
#endif
|
#endif
|
|
|
#ifdef OPT_EARLY_BRANCHING
|
#ifdef OPT_EARLY_BRANCHING
|
printw(" %s%s",
|
printw(" %s",
|
(m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":" ",
|
(m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)?"EB":" ");
|
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ");
|
|
#endif
|
#endif
|
|
|
/*
|
/*
|
showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
|
showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
|
mvprintw(ln, 17, "%s%s",
|
mvprintw(ln, 17, "%s%s",
|
| Line 226... |
Line 234... |
showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
|
showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
|
} else {
|
} else {
|
showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
|
showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
|
}
|
}
|
|
|
showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3));
|
showval(ln,60, "PIC2", m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state, (m_cursor==3));
|
|
|
ln++;
|
ln++;
|
showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
|
showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
|
showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
|
showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
|
showval(ln,40, "TMRB", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
|
showval(ln,40, "TMRC", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
|
showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
|
showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
|
|
|
|
|
if (!m_show_user_timers) {
|
if (!m_show_user_timers) {
|
ln++;
|
ln++;
|
| Line 296... |
Line 304... |
(m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
|
(m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
|
(m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
|
showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
|
showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
|
|
mvprintw(ln,60,"%s",
|
|
(m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
|
|
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
|
|
?"V"
|
|
:(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
|
|
&&(!m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
|
|
:" "));
|
ln++;
|
ln++;
|
|
|
if (m_core->v__DOT__thecpu__DOT__gie)
|
if (m_core->v__DOT__thecpu__DOT__gie)
|
attron(A_BOLD);
|
attron(A_BOLD);
|
else
|
else
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
mvprintw(ln, 0, "User Registers"); ln++;
|
mvprintw(ln, 0, "User Registers");
|
|
mvprintw(ln, 42, "DCDR=%02x %s%s",
|
|
dcdR(),
|
|
(m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ",
|
|
(m_core->v__DOT__thecpu__DOT__dcdF_wr)?"F":" ");
|
|
mvprintw(ln, 62, "OPR =%02x %s%s",
|
|
m_core->v__DOT__thecpu__DOT__opR,
|
|
(m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
|
|
(m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
|
|
ln++;
|
showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
|
showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
|
showreg(ln,20, "uR1 ", 17, (m_cursor==29));
|
showreg(ln,20, "uR1 ", 17, (m_cursor==29));
|
showreg(ln,40, "uR2 ", 18, (m_cursor==30));
|
showreg(ln,40, "uR2 ", 18, (m_cursor==30));
|
showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
|
showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
|
|
|
| Line 322... |
Line 346... |
|
|
showreg(ln, 0, "uR12", 28, (m_cursor==40));
|
showreg(ln, 0, "uR12", 28, (m_cursor==40));
|
showreg(ln,20, "uSP ", 29, (m_cursor==41));
|
showreg(ln,20, "uSP ", 29, (m_cursor==41));
|
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
|
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
|
(m_cursor == 42)?'>':' ',
|
(m_cursor == 42)?'>':' ',
|
(m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
|
(m_core->v__DOT__thecpu__DOT__trap)?"TP":" ",
|
(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
|
(m_core->v__DOT__thecpu__DOT__step)?"ST":" ",
|
(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
|
(m_core->v__DOT__thecpu__DOT__sleep)?"SL":" ",
|
(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ",
|
(m_core->v__DOT__thecpu__DOT__gie)?"IE":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
|
(m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
|
(m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
|
showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
|
showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
|
|
mvprintw(ln,60,"%s",
|
|
(m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
|
|
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
|
|
?"V"
|
|
:(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
|
|
&&(m_core->v__DOT__thecpu__DOT__alu_gie))?"+"
|
|
:" "));
|
|
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
ln+=1;
|
ln+=1;
|
|
|
#ifdef OPT_SINGLE_FETCH
|
#ifdef OPT_SINGLE_FETCH
|
ln+=2;
|
ln++;
|
|
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ",
|
|
(m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":" ",
|
|
" ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":" ",
|
|
(m_core->v__DOT__thecpu__DOT__pf_addr),
|
|
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
|
|
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
|
|
" ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ",
|
|
(m_core->v__DOT__wb_data)); ln++;
|
#else
|
#else
|
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
|
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
|
mvprintw(ln, 0, "PFCACH: v=%08x, %s, tag=%08x, pf_pc=%08x, lastpc=%08x",
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base,
|
(m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__tagval,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid,
|
m_core->v__DOT__thecpu__DOT__pf_pc,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting,
|
m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
|
m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv,
|
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
|
|
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff);
|
|
ln++;
|
ln++;
|
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":" ",
|
" ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":" ",
|
" ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_addr),
|
(m_core->v__DOT__thecpu__DOT__pf_addr),
|
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
|
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
|
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
|
(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ",
|
(pfstall())?"STL":" ",
|
(m_core->v__DOT__wb_data)); ln++;
|
(m_core->v__DOT__wb_data)); ln++;
|
#endif
|
#endif
|
|
|
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
|
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
|
| Line 382... |
Line 420... |
(mem_pipe_stalled())?'S':'-'); ln++;
|
(mem_pipe_stalled())?'S':'-'); ln++;
|
#else
|
#else
|
ln++;
|
ln++;
|
#endif
|
#endif
|
|
|
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
|
(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
|
(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
|
(m_core->o_wb_cyc)?"CYC":" ",
|
(m_core->o_wb_cyc)?"CYC":" ",
|
(m_core->o_wb_stb)?"STB":" ",
|
(m_core->o_wb_stb)?"STB":" ",
|
(m_core->o_wb_we )?"WE":" ",
|
(m_core->o_wb_we )?"WE":" ",
|
(m_core->o_wb_addr),
|
(m_core->o_wb_addr),
|
(m_core->o_wb_data),
|
(m_core->o_wb_data),
|
(m_core->i_wb_ack)?"ACK":" ",
|
(m_core->i_wb_ack)?"ACK":" ",
|
(m_core->i_wb_stall)?"STL":" ",
|
(m_core->i_wb_stall)?"STL":" ",
|
(m_core->i_wb_data)); ln+=2;
|
(m_core->i_wb_data),
|
|
(m_core->i_wb_err)?"(ER!)":" "); ln+=2;
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
|
mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
|
(m_core->v__DOT__thecpu__DOT__mem_ce),
|
(m_core->v__DOT__thecpu__DOT__mem_ce),
|
(m_core->v__DOT__thecpu__DOT__master_ce), //1
|
(m_core->v__DOT__thecpu__DOT__master_ce), //1
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem), //0
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem), //0
|
| Line 406... |
Line 445... |
(mem_stalled()),
|
(mem_stalled()),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__master_ce),
|
(m_core->v__DOT__thecpu__DOT__master_ce),
|
(mem_pipe_stalled()),
|
(mem_pipe_stalled()),
|
(!m_core->v__DOT__thecpu__DOT__op_pipe),
|
(!m_core->v__DOT__thecpu__DOT__op_pipe),
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
|
(m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
|
(m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
|
#else
|
|
(m_core->v__DOT__thecpu__DOT__mem_busy)
|
|
#endif
|
|
);
|
);
|
printw(" op_pipe = %d%d%d%d%d(%d|%d)",
|
printw(" op_pipe = %d%d%d%d%d(%d|%d)",
|
(m_core->v__DOT__thecpu__DOT__dcdvalid),
|
(dcdvalid()),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__dcdM),
|
(m_core->v__DOT__thecpu__DOT__dcdM),
|
(!((m_core->v__DOT__thecpu__DOT__dcdOp
|
(!((m_core->v__DOT__thecpu__DOT__dcdOp
|
^m_core->v__DOT__thecpu__DOT__opn)&1)),
|
^m_core->v__DOT__thecpu__DOT__opn)&1)),
|
(m_core->v__DOT__thecpu__DOT__dcdB
|
((int)(dcdB()&0x01f)
|
== m_core->v__DOT__thecpu__DOT__op_B),
|
== m_core->v__DOT__thecpu__DOT__op_B),
|
(m_core->v__DOT__thecpu__DOT__r_dcdI
|
(m_core->v__DOT__thecpu__DOT__dcdI
|
== m_core->v__DOT__thecpu__DOT__r_opI),
|
== m_core->v__DOT__thecpu__DOT__r_opI),
|
(m_core->v__DOT__thecpu__DOT__r_dcdI+1
|
(m_core->v__DOT__thecpu__DOT__dcdI+1
|
== m_core->v__DOT__thecpu__DOT__r_opI));
|
== m_core->v__DOT__thecpu__DOT__r_opI));
|
mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
|
mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
|
(m_core->v__DOT__thecpu__DOT__r_dcdI),
|
(m_core->v__DOT__thecpu__DOT__dcdI),
|
(m_core->v__DOT__thecpu__DOT__r_opI));
|
(m_core->v__DOT__thecpu__DOT__r_opI));
|
#endif
|
#endif
|
mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
|
mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
|
#ifdef OPT_SINGLE_CYCLE
|
#ifdef OPT_SINGLE_CYCLE
|
printw(" A:%c%c B:%c%c",
|
printw(" A:%c%c B:%c%c",
|
(m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
|
(m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
|
(m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
|
(m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
|
(m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
|
(m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-',
|
(m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
|
(m_core->v__DOT__thecpu__DOT__opB_mem)?'M':'-');
|
|
#else
|
|
printw(" A:xx B:xx");
|
#endif
|
#endif
|
|
printw(" PFPC=%08x", m_core->v__DOT__thecpu__DOT__pf_pc);
|
|
|
|
|
showins(ln, "I ",
|
showins(ln, "I ",
|
|
#ifdef OPT_PIPELINED
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
|
#else
|
|
1,
|
|
#endif
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
//m_core->v__DOT__thecpu__DOT__instruction_gie,
|
//m_core->v__DOT__thecpu__DOT__instruction_gie,
|
m_core->v__DOT__thecpu__DOT__gie,
|
m_core->v__DOT__thecpu__DOT__gie,
|
0,
|
0,
|
m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
|
|
showins(ln, "Dc",
|
showins(ln, "Dc",
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
dcd_ce(), dcdvalid(),
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
|
#ifdef OPT_PIPELINED
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
|
#else
|
|
0,
|
|
#endif
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
#ifdef OPT_ILLEGAL_INSTRUCTION
|
#ifdef OPT_ILLEGAL_INSTRUCTION
|
if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
|
if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
|
mvprintw(ln-1,10,"I");
|
mvprintw(ln-1,10,"I");
|
else
|
else
|
#endif
|
#endif
|
if (m_core->v__DOT__thecpu__DOT__dcdM)
|
if (m_core->v__DOT__thecpu__DOT__dcdM)
|
mvprintw(ln-1,10,"M");
|
mvprintw(ln-1,10,"M");
|
|
|
showins(ln, "Op",
|
showins(ln, "Op",
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
op_ce(),
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
op_pc()); ln++;
|
op_pc()); ln++;
|
#ifdef OPT_ILLEGAL_INSTRUCTION
|
#ifdef OPT_ILLEGAL_INSTRUCTION
|
| Line 481... |
Line 526... |
|
|
showins(ln, "Al",
|
showins(ln, "Al",
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
|
#ifdef OPT_PIPELINED
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
|
#else
|
|
0,
|
|
#endif
|
alu_pc()); ln++;
|
alu_pc()); ln++;
|
if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
|
if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
|
mvprintw(ln-1,10,"W");
|
mvprintw(ln-1,10,"W");
|
else if (m_core->v__DOT__thecpu__DOT__alu_valid)
|
else if (m_core->v__DOT__thecpu__DOT__alu_valid)
|
mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
|
mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wr)?"w":"V");
|
| Line 559... |
Line 608... |
printf("cpu-dbg-stall = %d\n", m_core->v__DOT__cpu_dbg_stall);
|
printf("cpu-dbg-stall = %d\n", m_core->v__DOT__cpu_dbg_stall);
|
printf("pf_cyc = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
|
printf("pf_cyc = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
|
printf("mem_cyc_gbl = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
|
printf("mem_cyc_gbl = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_gbl);
|
printf("mem_cyc_lcl = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
|
printf("mem_cyc_lcl = %d\n", m_core->v__DOT__thecpu__DOT__mem_cyc_lcl);
|
printf("opvalid = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
|
printf("opvalid = %d\n", m_core->v__DOT__thecpu__DOT__opvalid);
|
printf("dcdvalid = %d\n", m_core->v__DOT__thecpu__DOT__dcdvalid);
|
printf("dcdvalid = %d\n", dcdvalid()?1:0);
|
printf("dcd_ce = %d\n", m_core->v__DOT__thecpu__DOT__dcd_ce);
|
printf("dcd_ce = %d\n", dcd_ce()?1:0);
|
|
#ifdef OPT_PIPELINED
|
printf("dcd_stalled = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
|
printf("dcd_stalled = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
|
|
#endif
|
printf("pf_valid = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
|
printf("pf_valid = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
|
printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch);
|
#ifdef OPT_EARLY_BRANCHING
|
printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb);
|
// printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
|
|
#endif
|
|
|
exit(-2);
|
exit(-2);
|
}
|
}
|
|
|
assert(errcount < MAXERR);
|
assert(errcount < MAXERR);
|
| Line 695... |
Line 747... |
|
|
if (gie)
|
if (gie)
|
attron(A_BOLD);
|
attron(A_BOLD);
|
else
|
else
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
mvprintw(ln, 0, "User Registers"); ln++;
|
mvprintw(ln, 0, "User Registers");
|
|
mvprintw(ln, 42, "DCDR=%02x %s",
|
|
dcdR(), (m_core->v__DOT__thecpu__DOT__dcdR_wr)?"W":" ");
|
|
mvprintw(ln, 62, "OPR =%02x %s%s",
|
|
m_core->v__DOT__thecpu__DOT__opR,
|
|
(m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
|
|
(m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
|
|
ln++;
|
dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
|
dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
|
dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
|
dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
|
dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
|
dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
|
dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
|
dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
|
|
|
| Line 732... |
Line 791... |
ln+=2;
|
ln+=2;
|
|
|
ln+=3;
|
ln+=3;
|
|
|
showins(ln, "I ",
|
showins(ln, "I ",
|
|
#ifdef OPT_PIPELINED
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
|
#else
|
|
1,
|
|
#endif
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
m_core->v__DOT__thecpu__DOT__pf_valid,
|
m_core->v__DOT__thecpu__DOT__gie,
|
m_core->v__DOT__thecpu__DOT__gie,
|
0,
|
0,
|
m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
|
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
|
|
|
showins(ln, "Dc",
|
showins(ln, "Dc",
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
dcd_ce(), dcdvalid(),
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
|
#ifdef OPT_PIPELINED
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
|
#else
|
|
0,
|
|
#endif
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
|
|
|
showins(ln, "Op",
|
showins(ln, "Op",
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
op_ce(),
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
op_pc()); ln++;
|
op_pc()); ln++;
|
|
|
showins(ln, "Al",
|
showins(ln, "Al",
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
|
#ifdef OPT_PIPELINED
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
|
#else
|
|
0,
|
|
#endif
|
alu_pc()); ln++;
|
alu_pc()); ln++;
|
}
|
}
|
|
|
void tick(void) {
|
void tick(void) {
|
int gie = m_core->v__DOT__thecpu__DOT__gie;
|
int gie = m_core->v__DOT__thecpu__DOT__gie;
|
/*
|
/*
|
m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
|
m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
|
m_core->o_qspi_sck,
|
m_core->o_qspi_sck,
|
| Line 787... |
Line 858... |
(m_core->o_dbg_ack)?"ACK":" ",
|
(m_core->o_dbg_ack)?"ACK":" ",
|
(m_core->o_dbg_stall)?"STALL":" ",
|
(m_core->o_dbg_stall)?"STALL":" ",
|
(m_core->o_dbg_data),
|
(m_core->o_dbg_data),
|
(m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
|
(m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
|
(m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
|
(m_core->v__DOT__cpu_dbg_stall)?"CPU-DBG_STALL":"",
|
(m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"",
|
(dcdvalid())?"DCDV ":"",
|
(m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
|
(m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"",
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
|
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
|
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":" ",
|
(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":" ",
|
(m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
|
(m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"",
|
| Line 809... |
Line 880... |
(m_core->v__DOT__wb_data));
|
(m_core->v__DOT__wb_data));
|
}
|
}
|
|
|
if (dbg_fp)
|
if (dbg_fp)
|
fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d Reg=%02x, IPC=%08x, UPC=%08x\n",
|
fprintf(dbg_fp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d Reg=%02x, IPC=%08x, UPC=%08x\n",
|
m_core->v__DOT__thecpu__DOT__dcd_ce,
|
dcd_ce(),
|
m_core->v__DOT__thecpu__DOT__dcd_pc,
|
m_core->v__DOT__thecpu__DOT__dcd_pc,
|
m_core->v__DOT__thecpu__DOT__op_ce,
|
op_ce(),
|
op_pc(),
|
op_pc(),
|
m_core->v__DOT__thecpu__DOT__dcdA,
|
dcdA()&0x01f,
|
m_core->v__DOT__thecpu__DOT__opR,
|
m_core->v__DOT__thecpu__DOT__opR,
|
m_core->v__DOT__cmd_halt,
|
m_core->v__DOT__cmd_halt,
|
m_core->v__DOT__cpu_halt,
|
m_core->v__DOT__cpu_halt,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
m_core->v__DOT__thecpu__DOT__alu_valid,
|
| Line 826... |
Line 897... |
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__upc);
|
m_core->v__DOT__thecpu__DOT__upc);
|
|
|
if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
|
if ((dbg_fp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
|
fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
|
fprintf(dbg_fp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
|
m_core->v__DOT__pic_interrupt,
|
m_core->v__DOT__genblk9__DOT__pic__DOT__r_interrupt,
|
m_core->v__DOT__thecpu__DOT__wr_reg_ce,
|
m_core->v__DOT__thecpu__DOT__wr_reg_ce,
|
m_core->v__DOT__thecpu__DOT__wr_reg_id,
|
m_core->v__DOT__thecpu__DOT__wr_reg_id,
|
m_core->v__DOT__thecpu__DOT__wr_reg_vl,
|
m_core->v__DOT__thecpu__DOT__wr_reg_vl,
|
m_core->v__DOT__cmd_addr,
|
m_core->v__DOT__cmd_addr,
|
m_core->v__DOT__dbg_idata,
|
m_core->v__DOT__dbg_idata,
|
| Line 904... |
Line 975... |
(gie)?"Supervisor":"User",
|
(gie)?"Supervisor":"User",
|
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__ipc,
|
m_core->v__DOT__thecpu__DOT__upc,
|
m_core->v__DOT__thecpu__DOT__upc,
|
m_core->v__DOT__thecpu__DOT__pf_pc);
|
m_core->v__DOT__thecpu__DOT__pf_pc);
|
} if (dbg_fp) {
|
} if (dbg_fp) {
|
dbgins("Dc - ", m_core->v__DOT__thecpu__DOT__dcd_ce,
|
#ifdef NEW_PREFETCH_VERSION
|
m_core->v__DOT__thecpu__DOT__dcdvalid,
|
fprintf(dbg_fp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s\n",
|
|
(m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
|
|
m_core->v__DOT__thecpu__DOT__pf_pc,
|
|
m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_branch_pc,
|
|
((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)
|
|
&&(dcdvalid())
|
|
&&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
|
|
m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
|
|
m_core->v__DOT__thecpu__DOT__instruction_pc,
|
|
(m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
|
|
(m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ");
|
|
#endif
|
|
dbgins("Dc - ",
|
|
dcd_ce(), dcdvalid(),
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
m_core->v__DOT__thecpu__DOT__dcd_gie,
|
|
#ifdef OPT_PIPELINED
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
m_core->v__DOT__thecpu__DOT__dcd_stalled,
|
|
#else
|
|
0,
|
|
#endif
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1);
|
m_core->v__DOT__thecpu__DOT__dcd_pc-1);
|
dbgins("Op - ", m_core->v__DOT__thecpu__DOT__op_ce,
|
dbgins("Op - ",
|
|
op_ce(),
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__opvalid,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_gie,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
m_core->v__DOT__thecpu__DOT__op_stall,
|
op_pc());
|
op_pc());
|
/*
|
/*
|
| Line 940... |
Line 1029... |
*/
|
*/
|
dbgins("Al - ",
|
dbgins("Al - ",
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_ce,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
m_core->v__DOT__thecpu__DOT__alu_gie,
|
|
#ifdef OPT_PIPELINED
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
m_core->v__DOT__thecpu__DOT__alu_stall,
|
|
#else
|
|
0,
|
|
#endif
|
alu_pc());
|
alu_pc());
|
|
|
}
|
}
|
|
|
if ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
|
if ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
|
| Line 973... |
Line 1066... |
return r;
|
return r;
|
*/
|
*/
|
return m_core->v__DOT__thecpu__DOT__op_pc-1;
|
return m_core->v__DOT__thecpu__DOT__op_pc-1;
|
}
|
}
|
|
|
|
bool dcd_ce(void) {
|
|
#ifdef OPT_PIPELINED
|
|
return (m_core->v__DOT__thecpu__DOT__dcd_ce != 0);
|
|
#else
|
|
return (m_core->v__DOT__thecpu__DOT__pf_valid);
|
|
#endif
|
|
} bool dcdvalid(void) {
|
|
return (m_core->v__DOT__thecpu__DOT__r_dcdvalid !=0);
|
|
}
|
|
bool pfstall(void) {
|
|
return((!(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner))
|
|
||(m_core->v__DOT__cpu_stall));
|
|
}
|
|
unsigned dcdR(void) {
|
|
return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14);
|
|
}
|
|
unsigned dcdA(void) {
|
|
return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15);
|
|
}
|
|
unsigned dcdB(void) {
|
|
return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16);
|
|
}
|
|
|
|
bool op_ce(void) {
|
|
#ifdef OPT_PIPELINED
|
|
return (m_core->v__DOT__thecpu__DOT__op_ce != 0);
|
|
#else
|
|
// return (dcdvalid())&&(opvalid())
|
|
// &&(m_core->v__DOT__thecpu__DOT__op_stall);
|
|
return dcdvalid();
|
|
#endif
|
|
} bool opvalid(void) {
|
|
return (m_core->v__DOT__thecpu__DOT__opvalid !=0);
|
|
}
|
|
|
bool mem_busy(void) {
|
bool mem_busy(void) {
|
// return m_core->v__DOT__thecpu__DOT__mem_busy;
|
// return m_core->v__DOT__thecpu__DOT__mem_busy;
|
|
#ifdef OPT_PIPELINED
|
return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
|
return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
|
|
#else
|
|
return 0;
|
|
#endif
|
}
|
}
|
|
|
bool mem_stalled(void) {
|
bool mem_stalled(void) {
|
bool a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
|
bool a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
|
|
|
wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
|
wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
|
wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
|
wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
|
op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
|
op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
|
|
|
a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
b = (m_core->v__DOT__thecpu__DOT__op_pipe)&&(mem_busy());
|
//a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
|
|
a = mem_pipe_stalled();
|
|
b = (!m_core->v__DOT__thecpu__DOT__op_pipe)&&(mem_busy());
|
|
#else
|
|
a = false;
|
|
b = false;
|
|
#endif
|
d = ((wr_write_pc)||(wr_write_cc));
|
d = ((wr_write_pc)||(wr_write_cc));
|
c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
|
c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
|
&&((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)==op_gie)
|
&&(((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)?true:false)==op_gie)
|
&&d);
|
&&d);
|
d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
|
d =(m_core->v__DOT__thecpu__DOT__opvalid_mem)&&((a)||(b)||(c));
|
return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
|
return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
|
}
|
}
|
|
|
| Line 1006... |
Line 1144... |
*/
|
*/
|
return m_core->v__DOT__thecpu__DOT__alu_pc-1;
|
return m_core->v__DOT__thecpu__DOT__alu_pc-1;
|
}
|
}
|
|
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
int mem_pipe_stalled(void) {
|
bool mem_pipe_stalled(void) {
|
int r = 0;
|
int r = 0;
|
r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
|
r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
|
||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
|
||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
|
r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
|
r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
|
||(
|
||(
|
| Line 1193... |
Line 1331... |
if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
|
if (!tb->m_core->v__DOT__thecpu__DOT__gie) {
|
tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
|
tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
|
tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
|
tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
|
tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
|
tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
|
tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
|
tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
|
|
#ifdef OPT_PIPELINED
|
tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
|
tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
|
tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
|
tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
|
|
#endif
|
tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
|
tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
|
}
|
}
|
break;
|
break;
|
case 31:
|
case 31:
|
tb->m_core->v__DOT__thecpu__DOT__upc = v;
|
tb->m_core->v__DOT__thecpu__DOT__upc = v;
|
if (tb->m_core->v__DOT__thecpu__DOT__gie) {
|
if (tb->m_core->v__DOT__thecpu__DOT__gie) {
|
tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
|
tb->m_core->v__DOT__thecpu__DOT__pf_pc = v;
|
tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
|
tb->m_core->v__DOT__thecpu__DOT__new_pc = 1;
|
tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
|
tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
|
tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
|
tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
|
|
#ifdef OPT_PIPELINED
|
tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
|
tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
|
tb->m_core->v__DOT__thecpu__DOT__dcdvalid = 0;
|
tb->m_core->v__DOT__thecpu__DOT__r_dcdvalid = 0;
|
|
#endif
|
tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
|
tb->m_core->v__DOT__thecpu__DOT__opvalid = 0;
|
}
|
}
|
break;
|
break;
|
case 32: tb->m_core->v__DOT__pic_data = v; break;
|
case 32: tb->m_core->v__DOT__pic_data = v; break;
|
case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
|
case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
|
// case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
|
// case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
|
case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break;
|
case 35: tb->m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state = v; break;
|
case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
|
case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
|
case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
|
case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
|
case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
|
case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
|
case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
|
case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
|
case 44: tb->m_core->v__DOT__utc_data = v; break;
|
case 44: tb->m_core->v__DOT__utc_data = v; break;
|
| Line 1365... |
Line 1507... |
initscr();
|
initscr();
|
raw();
|
raw();
|
noecho();
|
noecho();
|
keypad(stdscr, true);
|
keypad(stdscr, true);
|
|
|
tb->reset();
|
// tb->reset();
|
for(int i=0; i<2; i++)
|
// for(int i=0; i<2; i++)
|
tb->tick();
|
// tb->tick();
|
|
tb->m_core->v__DOT__cmd_reset = 1;
|
tb->m_core->v__DOT__cmd_halt = 0;
|
tb->m_core->v__DOT__cmd_halt = 0;
|
|
|
int chv = 'q';
|
int chv = 'q';
|
|
|
bool done = false, halted = true, manual = true,
|
bool done = false, halted = true, manual = true,
|
