OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [cpp/] [zippy_tb.cpp] - Diff between revs 8 and 9

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 8 Rev 9
Line 34... Line 34...
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
//
//
#include <signal.h>
#include <signal.h>
#include <time.h>
#include <time.h>
 
#include <unistd.h>
 
 
#include <ctype.h>
#include <ctype.h>
#include <ncurses.h>
#include <ncurses.h>
 
 
#include "verilated.h"
#include "verilated.h"
Line 60... Line 61...
 
 
 
 
// No particular "parameters" need definition or redefinition here.
// No particular "parameters" need definition or redefinition here.
class   ZIPPY_TB : public TESTB<Vzipsystem> {
class   ZIPPY_TB : public TESTB<Vzipsystem> {
public:
public:
        unsigned long   m_tx_busy_count;
        unsigned long   m_mem_size;
        MEMSIM          m_mem;
        MEMSIM          m_mem;
        // QSPIFLASHSIM m_flash;
        // QSPIFLASHSIM m_flash;
        FILE            *dbg_fp;
        FILE            *dbg_fp;
        bool            dbg_flag, bomb;
        bool            dbg_flag, bomb;
 
 
        ZIPPY_TB(void) : m_mem(1<<20) {
        ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
                //dbg_fp = fopen("dbg.txt", "w");
                //dbg_fp = fopen("dbg.txt", "w");
                dbg_fp = NULL;
                dbg_fp = NULL;
                dbg_flag = false;
                dbg_flag = false;
                bomb = false;
                bomb = false;
        }
        }
Line 184... Line 185...
                showval(ln,41, "TMRB", m_core->v__DOT__timer_c__DOT__r_value);
                showval(ln,41, "TMRB", m_core->v__DOT__timer_c__DOT__r_value);
                showval(ln,61, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter);
                showval(ln,61, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter);
 
 
                ln++;
                ln++;
                showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
                showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
                showval(ln,21, "UMST", m_core->v__DOT__umc_data);
                showval(ln,21, "UOST", m_core->v__DOT__uoc_data);
                showval(ln,41, "UPST", m_core->v__DOT__upc_data);
                showval(ln,41, "UPST", m_core->v__DOT__upc_data);
                showval(ln,61, "UAST", m_core->v__DOT__uac_data);
                showval(ln,61, "UICT", m_core->v__DOT__uic_data);
 
 
                ln++;
                ln++;
                mvprintw(ln, 40, "%s %s",
                mvprintw(ln, 40, "%s %s",
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
Line 725... Line 726...
        noecho();
        noecho();
        keypad(stdscr, true);
        keypad(stdscr, true);
 
 
        // mem[0x00000] = 0xbe000010; // Halt instruction
        // mem[0x00000] = 0xbe000010; // Halt instruction
        unsigned int mptr = 0;
        unsigned int mptr = 0;
        /*
 
        tb->m_mem[mptr++] = 0x30000000; //  0: CLR R0
 
        tb->m_mem[mptr++] = 0x21000000; //  1: MOV R0,R1
 
        tb->m_mem[mptr++] = 0x22000001; //  2: MOV $1+R0,R2
 
        tb->m_mem[mptr++] = 0x23000002; //  3: MOV $2+R0,R3
 
        tb->m_mem[mptr++] = 0x24000022; //  4: MOV $22h+R0,R4
 
        tb->m_mem[mptr++] = 0x25100377; //  5: MOV $377h+R0,uR5
 
        tb->m_mem[mptr++] = 0x4e000000; //  6: NOOP
 
        tb->m_mem[mptr++] = 0xa0120000; //  7: ADD R2,R0
 
        tb->m_mem[mptr++] = 0xa0000020; //  8: ADD $32,R0
 
        tb->m_mem[mptr++] = 0xa00fffdf; //  9: ADD -$33,R0
 
        tb->m_mem[mptr++] = 0xc02fffff; //  A: NOT.Z R0
 
        tb->m_mem[mptr++] = 0xc0100000; //  B: CLRF R0
 
        tb->m_mem[mptr++] = 0x31000005; //  C: LDI $5,R1
 
        tb->m_mem[mptr++] = 0x00110000; //  D: CMP R0,R1
 
        tb->m_mem[mptr++] = 0xc0afffff; //  E: NOT.LT R0
 
        tb->m_mem[mptr++] = 0xc1cfffff; //  F: NOT.GE R1
 
        tb->m_mem[mptr++] = 0x621ffff9; // 10: LOD $-7(PC),R2
 
        tb->m_mem[mptr++] = 0x4f13dead; // 11: LODIHI $deadh,R3
 
        tb->m_mem[mptr++] = 0x4f03beef; // 12: LODILO $beefh,R3
 
        tb->m_mem[mptr++] = 0x731f0002; // 13: STO R3,$2(PC)
 
        */
 
 
 
        /*
 
        tb->m_mem[mptr++] = zp.op_clr(zp::ZIP_R12);//  0: CLR R12
 
        tb->m_mem[mptr++] = 0x4f1cc000; //  1: LODIHI $c000h,R12
 
        tb->m_mem[mptr++] = 0x2c1c0000; //  2: MOV R12,uR12
 
        tb->m_mem[mptr++] = 0x2f1f000a; //  3: MOV $12+PC,uPC
 
        tb->m_mem[mptr++] = 0x4f108001; //  4: LODIHI $8001,R0 // Turn on trap
 
        tb->m_mem[mptr++] = 0x4f00ffff; //  5: LODILO $ffff,R0 // interrupts
 
        tb->m_mem[mptr++] = 0x701c0001; //  6: STO R0,$1(R12)
 
        tb->m_mem[mptr++] = 0xbe000020; //  7: RTU      // Switch to user mode
 
        tb->m_mem[mptr++] = 0x601c0000; //  8: LOD (R12),R0 // Check the result
 
        tb->m_mem[mptr++] = 0x00000000; //  A: CMP $0,R0
 
        tb->m_mem[mptr++] = 0x2f4f0001; //  B: BNZ $1+PC
 
        tb->m_mem[mptr++] = 0xbe000010; //  C: HALT     // On SUCCESS
 
        tb->m_mem[mptr++] = 0x2f0f7fff; //  D: BRA PC-1 // On FAILURE
 
        */
 
 
 
 
 
 
        if (argc <= 1) {
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); //  0: CLR R0
        tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); //  0: CLR R0
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R0,zp.ZIP_R1); //  1: MOV R0,R1
        tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R0,zp.ZIP_R1); //  1: MOV R0,R1
        tb->m_mem[mptr++] = zp.op_mov(1,zp.ZIP_R0,zp.ZIP_R2); //  2: MOV $1+R0,R2
        tb->m_mem[mptr++] = zp.op_mov(1,zp.ZIP_R0,zp.ZIP_R2); //  2: MOV $1+R0,R2
        tb->m_mem[mptr++] = zp.op_mov(2,zp.ZIP_R0,zp.ZIP_R3); //  3: MOV $2+R0,R3
        tb->m_mem[mptr++] = zp.op_mov(2,zp.ZIP_R0,zp.ZIP_R3); //  3: MOV $2+R0,R3
        tb->m_mem[mptr++] = zp.op_mov(0x022, zp.ZIP_R0, zp.ZIP_R4); //  4: MOV $22h+R0,R4
        tb->m_mem[mptr++] = zp.op_mov(0x022, zp.ZIP_R0, zp.ZIP_R4); //  4: MOV $22h+R0,R4
Line 935... Line 898...
        tb->m_mem[mptr++] = zp.op_busy(); //  4: BRA PC-1
        tb->m_mem[mptr++] = zp.op_busy(); //  4: BRA PC-1
 
 
        // And, in case we miss a halt ...
        // And, in case we miss a halt ...
        tb->m_mem[mptr++] = zp.op_halt(); // HALT
        tb->m_mem[mptr++] = zp.op_halt(); // HALT
 
 
 
        } else {
 
                for(int argn=1; argn<argc; argn++) {
 
                        if (access(argv[argn], R_OK)==0) {
 
                                FILE *fp = fopen(argv[argn], "r");
 
                                if (fp == NULL) {
 
                                        printf("Cannot open %s\n", argv[argn]);
 
                                        perror("O/S Err: ");
 
                                        exit(-1);
 
                                } mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
 
                                fclose(fp);
 
                        }
 
                }
 
        }
 
 
        tb->reset();
        tb->reset();
        int     chv = 'q';
        int     chv = 'q';
        const   bool    live_debug_mode = true;
        const   bool    live_debug_mode = true;
 
 
        if (live_debug_mode) {
        if (live_debug_mode) {

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.