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% \graphicspath{{../gfx}}
% \graphicspath{{../gfx}}
\project{Zip CPU}
\project{Zip CPU}
\title{Specification}
\title{Specification}
\author{Dan Gisselquist, Ph.D.}
\author{Dan Gisselquist, Ph.D.}
\email{dgisselq (at) opencores.org}
\email{dgisselq (at) opencores.org}
\revision{Rev.~0.9}
\revision{Rev.~0.91}
\definecolor{webred}{rgb}{0.5,0,0}
\definecolor{webred}{rgb}{0.5,0,0}
\definecolor{webgreen}{rgb}{0,0.4,0}
\definecolor{webgreen}{rgb}{0,0.4,0}
\usepackage[dvips,ps2pdf,colorlinks=true,
 
        anchorcolor=black,pdfpagelabels,hypertexnames,
 
        pdfauthor={Dan Gisselquist},
 
        pdfsubject={Zip CPU}]{hyperref}
 
\hypersetup{
\hypersetup{
 
        ps2pdf,
 
        pdfpagelabels,
 
        hypertexnames,
 
        pdfauthor={Dan Gisselquist},
 
        pdfsubject={Zip CPU},
 
        anchorcolor= black,
        colorlinks = true,
        colorlinks = true,
        linkcolor  = webred,
        linkcolor  = webred,
        citecolor  = webgreen
        citecolor  = webgreen
}
}
\begin{document}
\begin{document}
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copy.
copy.
\end{license}
\end{license}
\begin{revisionhistory}
\begin{revisionhistory}
0.9 & 4/20/2016 & Gisselquist & Modified ISA: LDIHI replaced with MPY, MPYU and MPYS replaced with MPYUHI, and MPYSHI respectively.  LOCK instruction now
0.9 & 4/20/2016 & Gisselquist & Modified ISA: LDIHI replaced with MPY, MPYU and MPYS replaced with MPYUHI, and MPYSHI respectively.  LOCK instruction now
permits an intermediate ALU operation. \\\hline
permits an intermediate ALU operation. \\\hline
 
0.91& 7/16/2016 & Gisselquist & :escribed three more CC bits\\\hline
0.8 & 1/28/2016 & Gisselquist & Reduced complexity early branching \\\hline
0.8 & 1/28/2016 & Gisselquist & Reduced complexity early branching \\\hline
0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
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The status register is special, and bears further mention.  As shown in
The status register is special, and bears further mention.  As shown in
Fig.~\ref{tbl:cc-register},
Fig.~\ref{tbl:cc-register},
\begin{table}\begin{center}
\begin{table}\begin{center}
\begin{bitlist}
\begin{bitlist}
31\ldots 13 & R/W & Reserved for future uses\\\hline
31\ldots 23 & R & Reserved for future uses\\\hline
 
22\ldots 15 & R/W & Reserved for future uses\\\hline
 
14 & W & Clear I-Cache command\\\hline
 
13 & R & VLIW instruction phase (1 for first half)\\\hline
12 & R & (Reserved for) Floating Point Exception\\\hline
12 & R & (Reserved for) Floating Point Exception\\\hline
11 & R & Division by Zero Exception\\\hline
11 & R & Division by Zero Exception\\\hline
10 & R & Bus-Error Flag\\\hline
10 & R & Bus-Error Flag\\\hline
9 & R & Trap, or user interrupt, Flag.  Cleared on return to userspace.\\\hline
9 & R & Trap Flag (or user interrupt).  Cleared on return to userspace.\\\hline
8 & R & Illegal Instruction Flag\\\hline
8 & R & Illegal Instruction Flag\\\hline
7 & R/W & Break--Enable\\\hline
7 & R/W & Break--Enable (sCC), or user break (uCC)\\\hline
6 & R/W & Step\\\hline
6 & R/W & Step\\\hline
5 & R/W & Global Interrupt Enable (GIE)\\\hline
5 & R/W & Global Interrupt Enable (GIE)\\\hline
4 & R/W & Sleep.  When GIE is also set, the CPU waits for an interrupt.\\\hline
4 & R/W & Sleep.  When GIE is also set, the CPU waits for an interrupt.\\\hline
3 & R/W & Overflow\\\hline
3 & R/W & Overflow\\\hline
2 & R/W & Negative.  The sign bit was set as a result of the last ALU instruction.\\\hline
2 & R/W & Negative.  The sign bit was set as a result of the last ALU instruction.\\\hline
1 & R/W & Carry\\\hline
1 & R/W & Carry\\\hline
0 & R/W & Zero.  The last ALU operation produced a zero.\\\hline
0 & R/W & Zero.  The last ALU operation produced a zero.\\\hline
\end{bitlist}
\end{bitlist}
\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register}
\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register}
\end{center}\end{table}
\end{center}\end{table}
the lower 11~bits of the status register form
the lower 15~bits of the status register form
a set of CPU state and condition codes.  Writes to other bits of this register
a set of CPU state and condition codes.  Writes to other bits of this register
are preserved.
are preserved.
 
 
Of the condition codes, the bottom four bits are the current flags:
Of the condition codes, the bottom four bits are the current flags:
                Zero (Z),
                Zero (Z),
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        This functionality was added to enable a userspace debugger
        This functionality was added to enable a userspace debugger
        functionality on a user process, working through supervisor mode
        functionality on a user process, working through supervisor mode
        of course.
        of course.
 
 
 
 
The eighth bit is a break enable bit.  This controls whether a break
The eighth bit is a break enable bit.  When applied to the supervisor CC
instruction in user mode will halt the processor for an external debugger
register, this controls whether a break instruction in user mode will halt
(break enabled), or whether the break instruction will simply send send the
the processor for an external debugger (break enabled), or whether the break
CPU into interrupt mode.  Encountering a break in supervisor mode will
instruction will simply send send the CPU into interrupt mode.  Encountering
halt the CPU independent of the break enable bit.  This bit can only be set
a break in supervisor mode will halt the CPU independent of the break enable
within supervisor mode.
bit.  This bit can only be set within supervisor mode.  However, when applied
 
to the user CC register, from supervisor mode, this bit will indicate whether
 
or not the reason the CPU entered supervisor mode was from a break instruction
 
or not.  This break reason bit is automatically cleared upon any transition to
 
user mode, although it can also be cleared by the supervisor writing to the
 
user CC register.
 
 
% Should break enable be a supervisor mode bit, while the break enable bit
% Should break enable be a supervisor mode bit, while the break enable bit
% in user mode is a break has taken place bit?
% in user mode is a break has taken place bit?
%
%
 
 
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The tenth bit is a trap bit.  It is set whenever the user requests a soft
The tenth bit is a trap bit.  It is set whenever the user requests a soft
interrupt, and cleared on any return to userspace command.  This allows the
interrupt, and cleared on any return to userspace command.  This allows the
supervisor, in supervisor mode, to determine whether it got to supervisor
supervisor, in supervisor mode, to determine whether it got to supervisor
mode from a trap or from an external interrupt or both.
mode from a trap or from an external interrupt or both.
 
 
 
The eleventh bit is a bus error flag.  If the user program encountered a bus
 
error, this bit will be set in the user CC register and the CPU will switch to
 
supervisor mode.  The bit may be cleared by the supervisor, otherwise it is
 
automatically cleared upon any return to user mode.  If the supervisor
 
encounters a bus error, this bit will be set in the supervisor CC register
 
and the CPU will halt.  In that case, either a CPU reset or a write to the
 
supervisor CC register will clear this register.
 
 
 
The twelth bit is a division by zero exception flag.  This operates in a fashion
 
similar to the bus error flag.  If the user attempts to use the divide
 
instruction with a zero denominator, the system will switch to supervisor mode
 
and set this bit in the user CC register.  The bit is automatically cleared
 
upon any return to user mode, although it can also be manually cleared by
 
the supervisor.  In a similar fashion, if the supervisor attempts to execute
 
a divide by zero, the CPU will halt and set the zero exception flag in the
 
supervisor's CC register.  This will automatically be cleared upon any CPU
 
reset, or it may be manually cleared by the external debugger writing to this
 
register.
 
 
 
The thirteenth bit will operate in a similar fashion to both the bus error
 
and division by zero flags, only it will be set upon a (yet to be determined)
 
floating point error.
 
 
 
Finally, the fourteenth bit references a clear cache bit.  The supervisor may
 
write a one to this bit in order to clear the CPU instruction cache.  The
 
bit always reads as a zero.
 
 
 
Some of the upper bits have been temporarily assigned to indicate CPU
 
capabilities.  This is not a permanent feature, as these upper bits officially
 
remain reserved.
 
 
\section{Instruction Format}
\section{Instruction Format}
All Zip CPU instructions fit in one of the formats shown in
All Zip CPU instructions fit in one of the formats shown in
Fig.~\ref{fig:iset-format}.
Fig.~\ref{fig:iset-format}.
\begin{figure}\begin{center}
\begin{figure}\begin{center}
\begin{bytefield}[endianness=big]{32}
\begin{bytefield}[endianness=big]{32}
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15 & R/W & Set to `1' to trigger on an interrupt, or `0' to start immediately
15 & R/W & Set to `1' to trigger on an interrupt, or `0' to start immediately
        upon receiving a valid key.\\\hline
        upon receiving a valid key.\\\hline
14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline
14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline
9\ldots 0 & R/W & Intermediate transfer length minus one.  Thus, to transfer
9\ldots 0 & R/W & Intermediate transfer length minus one.  Thus, to transfer
        one item at a time set this value to 0. To transfer 1024 at a time,
        one item at a time set this value to 0. To transfer 1024 at a time,
        set it to 1024.\\\hline
        set it to 1023.\\\hline
\end{bitlist}
\end{bitlist}
\caption{DMA Control Register Bits}\label{tbl:dmacbits}
\caption{DMA Control Register Bits}\label{tbl:dmacbits}
\end{center}\end{table}
\end{center}\end{table}
This control register has been designed so that the common case of memory
This control register has been designed so that the common case of memory
access need only set the key and the transfer length.  Hence, writing a
access need only set the key and the transfer length.  Hence, writing a
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might wish to write \hbox{32'h2fed8000}--this assumes, of course, that you
might wish to write \hbox{32'h2fed8000}--this assumes, of course, that you
have a serial port wired to the zero bit of this interrupt control.  (The
have a serial port wired to the zero bit of this interrupt control.  (The
DMA controller does not use the interrupt controller, and cannot clear
DMA controller does not use the interrupt controller, and cannot clear
interrupts.)  As a third example, if you wished to write to an external
interrupts.)  As a third example, if you wished to write to an external
FIFO anytime it was less than half full (had fewer than 512 items), and
FIFO anytime it was less than half full (had fewer than 512 items), and
interrupt line 2 indicated this condition, you might wish to issue a
interrupt line 3 indicated this condition, you might wish to issue a
\hbox{32'h1fed8dff} to this port.
\hbox{32'h1fed8dff} to this port.
 
 
\section{Debug Port Registers}
\section{Debug Port Registers}
Accessing the Zip System via the debug port isn't as straight forward as
Accessing the Zip System via the debug port isn't as straight forward as
accessing the system via the wishbone bus.  The debug port itself has been
accessing the system via the wishbone bus.  The debug port itself has been

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