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had struggled with various timing violations to keep it at 100~MHz. So, for
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had struggled with various timing violations to keep it at 100~MHz. So, for
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now, I will only state that it can run at 100~MHz.
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now, I will only state that it can run at 100~MHz.
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\chapter{I/O Ports}\label{chap:ioports}
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\chapter{I/O Ports}\label{chap:ioports}
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The I/O ports for this clock are shown in Tbls.~\ref{tbl:iowishbone}
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\begin{table}[htbp]
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\begin{center}
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\begin{portlist}
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i\_clk & 1 & Input & System clock, used for time and wishbone interfaces.\\\hline
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i\_wb\_cyc & 1 & Input & Wishbone bus cycle wire.\\\hline
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i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline
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i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline
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i\_wb\_addr & 5 & Input & Wishbone address.\\\hline
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i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing
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(configuring) the core from the bus.\\\hline
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o\_wb\_ack & 1 & Output & Return value acknowledging a wishbone write, or
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signifying valid data in the case of a wishbone read request.
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\\\hline
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o\_wb\_stall & 1 & Output & Indicates the device is not yet ready for another
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wishbone access, effectively stalling the bus.\\\hline
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o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read
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from the interface.\\\hline
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\end{portlist}
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\caption{Wishbone I/O Ports}\label{tbl:iowishbone}
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\end{center}\end{table}
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and~Tbl.~\ref{tbl:ioother}.
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\begin{table}[htbp]
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\begin{center}
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\begin{portlist}
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o\_sseg & 32 & Output & Lines to control a seven segment display, to be
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sent to that display's driver. Each eight bit byte controls
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one digit in the display, with the bottom bit in the byte
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controlling the decimal point.\\\hline
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o\_led & 16 & Output & Output LED's, consisting of a 16--bit counter counting
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from zero to all ones each minute, and synchronized with each
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minute so as to create an indicator of when the next minute
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will take place when only the hours and minutes can be
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displayed.\\\hline
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o\_interrupt & 1 & Output & A pulsed/strobed interrupt line. When the
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clock needs to generate an interrupt, it will set this line
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high for one clock cycle. \\\hline
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o\_ppd & 1 & Output & A `pulse per day' signal which can be fed into the
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real--time date module. This line will be high on the clock before
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the stroke of midnight, allowing the date module to turn over to the
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next day at exactly the same time the clock module turns over to the
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next day.\\\hline
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i\_hack & 1 & Input & When this line is raised, copies are made of the
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internal state registers on the next clock. These registers can then
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be used for an accurate time hack regarding the state of the clock
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at the time this line was strobed.\\\hline
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\end{portlist}
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\caption{Other I/O Ports}\label{tbl:ioother}
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\end{center}\end{table}
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Tbl.~\ref{tbl:iowishbone} reiterates the wishbone I/O values just discussed in
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Chapt.~\ref{chap:wishbone}, and so need no further discussion here.
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% Appendices
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% Appendices
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% Index
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% Index
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\end{document}
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\end{document}
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