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The tenth bit is a trap bit.  It is set whenever the user requests a soft
The tenth bit is a trap bit.  It is set whenever the user requests a soft
interrupt, and cleared on any return to userspace command.  This allows the
interrupt, and cleared on any return to userspace command.  This allows the
supervisor, in supervisor mode, to determine whether it got to supervisor
supervisor, in supervisor mode, to determine whether it got to supervisor
mode from a trap or from an external interrupt or both.
mode from a trap or from an external interrupt or both.
 
 
These status register bits are summarized in Tbl.~\ref{tbl:ccbits}.
 
\begin{table}
 
\begin{center}
 
\begin{tabular}{l|l}
 
Bit & Meaning \\\hline
 
9 & Soft trap, set on a trap from user mode, cleared when returning to user mode\\\hline
 
8 & (Reserved for) Floating point enable \\\hline
 
7 & Halt on break, to support an external debugger \\\hline
 
6 & Step, single step the CPU in user mode\\\hline
 
5 & GIE, or Global Interrupt Enable \\\hline
 
4 & Sleep \\\hline
 
3 & V, or overflow bit.\\\hline
 
2 & N, or negative bit.\\\hline
 
1 & C, or carry bit.\\\hline
 
0 & Z, or zero bit. \\\hline
 
\end{tabular}
 
\caption{Condition Code / Status Register Bits}\label{tbl:ccbits}
 
\end{center}\end{table}
 
 
 
\section{Conditional Instructions}
\section{Conditional Instructions}
Most, although not quite all, instructions may be conditionally executed.  From
Most, although not quite all, instructions may be conditionally executed.  From
the four condition code flags, eight conditions are defined.  These are shown
the four condition code flags, eight conditions are defined.  These are shown
in Tbl.~\ref{tbl:conditions}.
in Tbl.~\ref{tbl:conditions}.
\begin{table}
\begin{table}
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        operations have consequences in that they might stall the bus if
        operations have consequences in that they might stall the bus if
        Rx isn't ready yet.  For this reason, we have a dedicated NOOP
        Rx isn't ready yet.  For this reason, we have a dedicated NOOP
        instruction. \\\hline
        instruction. \\\hline
NOT Rx & XOR \$-1,Rx & \\\hline
NOT Rx & XOR \$-1,Rx & \\\hline
POP Rx
POP Rx
        & \parbox[t]{1.5in}{LOD \$-1(SP),Rx \\ ADD \$1,SP}
        & \parbox[t]{1.5in}{LOD \$1(SP),Rx \\ ADD \$1,SP}
        & Note
        & Note
        that for interrupt purposes, one can never depend upon the value at
        that for interrupt purposes, one can never depend upon the value at
        (SP).  Hence you read from it, then increment it, lest having
        (SP).  Hence you read from it, then increment it, lest having
        incremented it first something then comes along and writes to that
        incremented it first something then comes along and writes to that
        value before you can read the result. \\\hline
        value before you can read the result. \\\hline
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        a TRAP bit within the CC register.  Therefore, upon entering the
        a TRAP bit within the CC register.  Therefore, upon entering the
        supervisor state, the CPU only need check this bit to know that it
        supervisor state, the CPU only need check this bit to know that it
        got there via a TRAP.  The trap could be made conditional by making
        got there via a TRAP.  The trap could be made conditional by making
        the LDI and the AND conditional.  In that case, the assembler would
        the LDI and the AND conditional.  In that case, the assembler would
        quietly turn the LDI instruction into an LDILO and LDIHI pair,
        quietly turn the LDI instruction into an LDILO and LDIHI pair,
        but the effectt would be the same. \\\hline
        but the effect would be the same. \\\hline
\end{tabular}
\end{tabular}
\caption{Derived Instructions, continued}\label{tbl:derived-3}
\caption{Derived Instructions, continued}\label{tbl:derived-3}
\end{center}\end{table}
\end{center}\end{table}
\begin{table}\begin{center}
\begin{table}\begin{center}
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

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