URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [Makefile] - Diff between revs 18 and 36

Rev 18	Rev 36
Line 36...	Line 36...

`CORED:= core`	`CORED:= core`
`PRPHD:= peripherals`	`PRPHD:= peripherals`
`AUXD := aux`	`AUXD := aux`
`VSRC := zipsystem.v \`	`VSRC := zipsystem.v \`
`$(PRPHD)/flashcache.v $(PRPHD)/icontrol.v \`	`$(PRPHD)/wbdmac.v $(PRPHD)/icontrol.v \`
`$(PRPHD)/zipcounter.v $(PRPHD)/zipjiffies.v \`	`$(PRPHD)/zipcounter.v $(PRPHD)/zipjiffies.v \`
`$(PRPHD)/ziptimer.v $(PRPHD)/ziptrap.v \`	`$(PRPHD)/ziptimer.v $(PRPHD)/ziptrap.v \`
`$(CORED)/zipcpu.v $(CORED)/cpuops.v \`	`$(CORED)/zipcpu.v $(CORED)/cpuops.v \`
`$(CORED)/pipefetch.v $(CORED)/prefetch.v \`	`$(CORED)/pipefetch.v $(CORED)/prefetch.v \`
`$(CORED)/memops.v \`	`$(CORED)/memops.v \`
`$(AUXD)/busdelay.v $(AUXD)/wbarbiter.v`	`$(AUXD)/busdelay.v $(AUXD)/wbarbiter.v \`
	`$(AUXD)/wbdblpriarb.v $(AUXD)/wbpriarbiter.v`

`VOBJ := obj_dir`	`VOBJ := obj_dir`

`$(VOBJ)/Vzipsystem.cpp: $(VSRC)`	`$(VOBJ)/Vzipsystem.cpp: $(VSRC)`
`verilator -cc -y $(CORED) -y $(PRPHD) -y $(AUXD) zipsystem.v`	`verilator -cc -y $(CORED) -y $(PRPHD) -y $(AUXD) zipsystem.v`