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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Diff between revs 2 and 15

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Rev 2 Rev 15
Line 85... Line 85...
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_wb_ack  <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
                o_wb_ack  <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_wb_data <= i_dly_data;
                o_wb_data <= i_dly_data;
 
 
        // Our only non-delayed line, yet still really delayed.
        // Our only non-delayed line, yet still really delayed.  Perhaps
        assign  o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall));
        // there's a way to register this?
 
        // o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
 
        assign  o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(~o_dly_stb));
 
 
endmodule
endmodule
 
 
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