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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Diff between revs 34 and 36

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Rev 34 Rev 36
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///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
module  busdelay(i_clk,
module  busdelay(i_clk,
                // The input bus
                // The input bus
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data,
                        o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
                // The delayed bus
                // The delayed bus
                o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data,
                o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data,
                        i_dly_ack, i_dly_stall, i_dly_data);
                        i_dly_ack, i_dly_stall, i_dly_data, i_dly_err);
        parameter       AW=32, DW=32;
        parameter       AW=32, DW=32;
        input   i_clk;
        input   i_clk;
        // Input/master bus
        // Input/master bus
        input                           i_wb_cyc, i_wb_stb, i_wb_we;
        input                           i_wb_cyc, i_wb_stb, i_wb_we;
        input           [(AW-1):0]       i_wb_addr;
        input           [(AW-1):0]       i_wb_addr;
        input           [(DW-1):0]       i_wb_data;
        input           [(DW-1):0]       i_wb_data;
        output  reg                     o_wb_ack;
        output  reg                     o_wb_ack;
        output  wire                    o_wb_stall;
        output  wire                    o_wb_stall;
        output  reg     [(DW-1):0]       o_wb_data;
        output  reg     [(DW-1):0]       o_wb_data;
 
        output  wire                    o_wb_err;
        // Delayed bus
        // Delayed bus
        output  reg                     o_dly_cyc, o_dly_stb, o_dly_we;
        output  reg                     o_dly_cyc, o_dly_stb, o_dly_we;
        output  reg     [(AW-1):0]       o_dly_addr;
        output  reg     [(AW-1):0]       o_dly_addr;
        output  reg     [(DW-1):0]       o_dly_data;
        output  reg     [(DW-1):0]       o_dly_data;
        input                           i_dly_ack;
        input                           i_dly_ack;
        input                           i_dly_stall;
        input                           i_dly_stall;
        input           [(DW-1):0]       i_dly_data;
        input           [(DW-1):0]       i_dly_data;
 
        input                           i_dly_err;
 
 
        initial o_dly_cyc = 1'b0;
        initial o_dly_cyc = 1'b0;
        initial o_dly_stb = 1'b0;
        initial o_dly_stb = 1'b0;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
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        // Our only non-delayed line, yet still really delayed.  Perhaps
        // Our only non-delayed line, yet still really delayed.  Perhaps
        // there's a way to register this?
        // there's a way to register this?
        // o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
        // o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
        assign  o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(o_dly_stb));
        assign  o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(o_dly_stb));
 
        assign  o_wb_err   = i_dly_err;
 
 
endmodule
endmodule
 
 
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