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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module busdelay(i_clk,
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module busdelay(i_clk,
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// The input bus
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// The input bus
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
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// The delayed bus
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// The delayed bus
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o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data,
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o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data,
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i_dly_ack, i_dly_stall, i_dly_data);
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i_dly_ack, i_dly_stall, i_dly_data, i_dly_err);
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parameter AW=32, DW=32;
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parameter AW=32, DW=32;
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input i_clk;
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input i_clk;
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// Input/master bus
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// Input/master bus
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [(AW-1):0] i_wb_addr;
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input [(AW-1):0] i_wb_addr;
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input [(DW-1):0] i_wb_data;
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input [(DW-1):0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [(DW-1):0] o_wb_data;
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output reg [(DW-1):0] o_wb_data;
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output wire o_wb_err;
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// Delayed bus
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// Delayed bus
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output reg o_dly_cyc, o_dly_stb, o_dly_we;
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output reg o_dly_cyc, o_dly_stb, o_dly_we;
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output reg [(AW-1):0] o_dly_addr;
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output reg [(AW-1):0] o_dly_addr;
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output reg [(DW-1):0] o_dly_data;
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output reg [(DW-1):0] o_dly_data;
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input i_dly_ack;
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input i_dly_ack;
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input i_dly_stall;
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input i_dly_stall;
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input [(DW-1):0] i_dly_data;
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input [(DW-1):0] i_dly_data;
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input i_dly_err;
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initial o_dly_cyc = 1'b0;
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initial o_dly_cyc = 1'b0;
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initial o_dly_stb = 1'b0;
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initial o_dly_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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// Our only non-delayed line, yet still really delayed. Perhaps
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// Our only non-delayed line, yet still really delayed. Perhaps
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// there's a way to register this?
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// there's a way to register this?
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// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(o_dly_stb));
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assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(o_dly_stb));
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assign o_wb_err = i_dly_err;
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endmodule
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endmodule
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