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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Diff between revs 36 and 61
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| Rev 36 |
Rev 61 |
| Line 70... |
Line 70... |
initial o_dly_cyc = 1'b0;
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initial o_dly_cyc = 1'b0;
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initial o_dly_stb = 1'b0;
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initial o_dly_stb = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_dly_cyc <= i_wb_cyc;
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o_dly_cyc <= i_wb_cyc;
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// Add the i_wb_cyc criteria here, so we can simplify the o_wb_stall
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// criteria below, which would otherwise *and* these two.
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_stall)
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if (~o_wb_stall)
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o_dly_stb <= i_wb_stb;
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o_dly_stb <= ((i_wb_cyc)&&(i_wb_stb));
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_stall)
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if (~o_wb_stall)
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o_dly_we <= i_wb_we;
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o_dly_we <= i_wb_we;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~o_wb_stall)
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if (~o_wb_stall)
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| Line 90... |
Line 92... |
o_wb_data <= i_dly_data;
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o_wb_data <= i_dly_data;
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// Our only non-delayed line, yet still really delayed. Perhaps
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// Our only non-delayed line, yet still really delayed. Perhaps
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// there's a way to register this?
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// there's a way to register this?
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// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(o_dly_stb));
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// assign o_wb_stall=((i_wb_cyc)&&(i_dly_stall)&&(o_dly_stb));//&&o_cyc
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assign o_wb_stall = ((i_dly_stall)&&(o_dly_stb));//&&o_cyc
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assign o_wb_err = i_dly_err;
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assign o_wb_err = i_dly_err;
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endmodule
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endmodule
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