OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Diff between revs 36 and 61

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 36 Rev 61
Line 70... Line 70...
        initial o_dly_cyc = 1'b0;
        initial o_dly_cyc = 1'b0;
        initial o_dly_stb = 1'b0;
        initial o_dly_stb = 1'b0;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                o_dly_cyc <= i_wb_cyc;
                o_dly_cyc <= i_wb_cyc;
 
        // Add the i_wb_cyc criteria here, so we can simplify the o_wb_stall
 
        // criteria below, which would otherwise *and* these two.
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (~o_wb_stall)
                if (~o_wb_stall)
                        o_dly_stb <= i_wb_stb;
                        o_dly_stb <= ((i_wb_cyc)&&(i_wb_stb));
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (~o_wb_stall)
                if (~o_wb_stall)
                        o_dly_we  <= i_wb_we;
                        o_dly_we  <= i_wb_we;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (~o_wb_stall)
                if (~o_wb_stall)
Line 90... Line 92...
                o_wb_data <= i_dly_data;
                o_wb_data <= i_dly_data;
 
 
        // Our only non-delayed line, yet still really delayed.  Perhaps
        // Our only non-delayed line, yet still really delayed.  Perhaps
        // there's a way to register this?
        // there's a way to register this?
        // o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
        // o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
        assign  o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(o_dly_stb));
        // assign o_wb_stall=((i_wb_cyc)&&(i_dly_stall)&&(o_dly_stb));//&&o_cyc
 
        assign  o_wb_stall = ((i_dly_stall)&&(o_dly_stb));//&&o_cyc
        assign  o_wb_err   = i_dly_err;
        assign  o_wb_err   = i_dly_err;
 
 
endmodule
endmodule
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.