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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [wbarbiter.v] - Diff between revs 69 and 180

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Rev 69 Rev 180
Line 112... Line 112...
        // first clock of the bus cycle
        // first clock of the bus cycle
        reg     r_a_owner, r_b_owner;
        reg     r_a_owner, r_b_owner;
        wire    w_a_owner, w_b_owner;
        wire    w_a_owner, w_b_owner;
`ifdef  WBA_ALTERNATING
`ifdef  WBA_ALTERNATING
        reg     r_a_last_owner;
        reg     r_a_last_owner;
        // Stall must be asserted on the same cycle the input master asserts
 
        // the bus, if the bus isn't granted to him.
 
        assign  o_a_stall = (w_a_owner) ? i_stall : 1'b1;
 
        assign  o_b_stall = (w_b_owner) ? i_stall : 1'b1;
 
 
 
`endif
`endif
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
                begin
Line 173... Line 169...
        // the master in question does not own the bus.  Hence we force it
        // the master in question does not own the bus.  Hence we force it
        // low if the particular master doesn't own the bus.
        // low if the particular master doesn't own the bus.
        assign  o_a_ack   = (w_a_owner) ? i_ack   : 1'b0;
        assign  o_a_ack   = (w_a_owner) ? i_ack   : 1'b0;
        assign  o_b_ack   = (w_b_owner) ? i_ack   : 1'b0;
        assign  o_b_ack   = (w_b_owner) ? i_ack   : 1'b0;
 
 
 
        // Stall must be asserted on the same cycle the input master asserts
 
        // the bus, if the bus isn't granted to him.
 
        assign  o_a_stall = (w_a_owner) ? i_stall : 1'b1;
 
        assign  o_b_stall = (w_b_owner) ? i_stall : 1'b1;
 
 
        //
        //
        //
        //
        assign  o_a_err = (w_a_owner) ? i_err : 1'b0;
        assign  o_a_err = (w_a_owner) ? i_err : 1'b0;
        assign  o_b_err = (w_b_owner) ? i_err : 1'b0;
        assign  o_b_err = (w_b_owner) ? i_err : 1'b0;
 
 

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