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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [wbarbiter.v] - Diff between revs 2 and 36

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///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
`define WBA_ALTERNATING
`define WBA_ALTERNATING
module  wbarbiter(i_clk, i_rst,
module  wbarbiter(i_clk, i_rst,
        // Bus A
        // Bus A
        i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall,
        i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall, o_a_err,
        // Bus B
        // Bus B
        i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall,
        i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall, o_b_err,
        // Both buses
        // Both buses
        o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall);
        o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall, i_err);
        // 18 bits will address one GB, 4 bytes at a time.
        // 18 bits will address one GB, 4 bytes at a time.
        // 19 bits will allow the ability to address things other than just
        // 19 bits will allow the ability to address things other than just
        // the 1GB of memory we are expecting.
        // the 1GB of memory we are expecting.
        parameter                       DW=32, AW=19;
        parameter                       DW=32, AW=19;
        // Wishbone doesn't use an i_ce signal.  While it could, they dislike
        // Wishbone doesn't use an i_ce signal.  While it could, they dislike
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        input                           i_clk, i_rst;
        input                           i_clk, i_rst;
        input           [(AW-1):0]       i_a_adr, i_b_adr;
        input           [(AW-1):0]       i_a_adr, i_b_adr;
        input           [(DW-1):0]       i_a_dat, i_b_dat;
        input           [(DW-1):0]       i_a_dat, i_b_dat;
        input                           i_a_we, i_a_stb, i_a_cyc;
        input                           i_a_we, i_a_stb, i_a_cyc;
        input                           i_b_we, i_b_stb, i_b_cyc;
        input                           i_b_we, i_b_stb, i_b_cyc;
        output  wire                    o_a_ack, o_b_ack, o_a_stall, o_b_stall;
        output  wire                    o_a_ack, o_b_ack, o_a_stall, o_b_stall,
 
                                        o_a_err, o_b_err;
        output  wire    [(AW-1):0]       o_adr;
        output  wire    [(AW-1):0]       o_adr;
        output  wire    [(DW-1):0]       o_dat;
        output  wire    [(DW-1):0]       o_dat;
        output  wire                    o_we, o_stb, o_cyc;
        output  wire                    o_we, o_stb, o_cyc;
        input                           i_ack, i_stall;
        input                           i_ack, i_stall, i_err;
 
 
        // All the fancy stuff here is done with the three primary signals:
        // All the fancy stuff here is done with the three primary signals:
        //      o_cyc
        //      o_cyc
        //      w_a_owner
        //      w_a_owner
        //      w_b_owner
        //      w_b_owner
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        // first clock of the bus cycle
        // first clock of the bus cycle
        reg     r_a_owner, r_b_owner;
        reg     r_a_owner, r_b_owner;
        wire    w_a_owner, w_b_owner;
        wire    w_a_owner, w_b_owner;
`ifdef  WBA_ALTERNATING
`ifdef  WBA_ALTERNATING
        reg     r_a_last_owner;
        reg     r_a_last_owner;
 
        // Stall must be asserted on the same cycle the input master asserts
 
        // the bus, if the bus isn't granted to him.
 
        assign  o_a_stall = (w_a_owner) ? i_stall : 1'b1;
 
        assign  o_b_stall = (w_b_owner) ? i_stall : 1'b1;
 
 
`endif
`endif
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
                begin
                        r_a_owner <= 1'b0;
                        r_a_owner <= 1'b0;
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        // the master in question does not own the bus.  Hence we force it
        // the master in question does not own the bus.  Hence we force it
        // low if the particular master doesn't own the bus.
        // low if the particular master doesn't own the bus.
        assign  o_a_ack   = (w_a_owner) ? i_ack   : 1'b0;
        assign  o_a_ack   = (w_a_owner) ? i_ack   : 1'b0;
        assign  o_b_ack   = (w_b_owner) ? i_ack   : 1'b0;
        assign  o_b_ack   = (w_b_owner) ? i_ack   : 1'b0;
 
 
        // Stall must be asserted on the same cycle the input master asserts
        //
        // the bus, if the bus isn't granted to him.
        //
        assign  o_a_stall = (w_a_owner) ? i_stall : 1'b1;
        assign  o_a_err = (w_a_owner) ? i_err : 1'b0;
        assign  o_b_stall = (w_b_owner) ? i_stall : 1'b1;
        assign  o_b_err = (w_b_owner) ? i_err : 1'b0;
 
 
endmodule
endmodule
 
 
 
 
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