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///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    wbdblpriarb.v
// Filename:    wbdblpriarb.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
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//
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
 
// You should have received a copy of the GNU General Public License along
 
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
 
// target there if the PDF file isn't present.)  If not, see
 
// <http://www.gnu.org/licenses/> for a copy.
 
//
// License:     GPL, v3, as defined and found on www.gnu.org,
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
 
//
//
//
module  wbdblpriarb(i_clk, i_rst,
module  wbdblpriarb(i_clk, i_rst,
        // Bus A
        // Bus A
        i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err,
        i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
        // Bus B
        // Bus B
        i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err,
        i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
        // Both buses
        // Both buses
        o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat,
        o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, o_sel,
                i_ack, i_stall, i_err);
                i_ack, i_stall, i_err);
        parameter                       DW=32, AW=32;
        parameter                       DW=32, AW=32;
        // Wishbone doesn't use an i_ce signal.  While it could, they dislike
        // Wishbone doesn't use an i_ce signal.  While it could, they dislike
        // what it would (might) do to the synchronous reset signal, i_rst.
        // what it would (might) do to the synchronous reset signal, i_rst.
        input                           i_clk, i_rst;
        input                           i_clk, i_rst;
        // Bus A
        // Bus A
        input                           i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we;
        input                           i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we;
        input           [(AW-1):0]       i_a_adr;
        input           [(AW-1):0]       i_a_adr;
        input           [(DW-1):0]       i_a_dat;
        input           [(DW-1):0]       i_a_dat;
 
        input           [(DW/8-1):0]     i_a_sel;
        output  wire                    o_a_ack, o_a_stall, o_a_err;
        output  wire                    o_a_ack, o_a_stall, o_a_err;
        // Bus B
        // Bus B
        input                           i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we;
        input                           i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we;
        input           [(AW-1):0]       i_b_adr;
        input           [(AW-1):0]       i_b_adr;
        input           [(DW-1):0]       i_b_dat;
        input           [(DW-1):0]       i_b_dat;
 
        input           [(DW/8-1):0]     i_b_sel;
        output  wire                    o_b_ack, o_b_stall, o_b_err;
        output  wire                    o_b_ack, o_b_stall, o_b_err;
        // 
        // 
        output  wire                    o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we;
        output  wire                    o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we;
        output  wire    [(AW-1):0]       o_adr;
        output  wire    [(AW-1):0]       o_adr;
        output  wire    [(DW-1):0]       o_dat;
        output  wire    [(DW-1):0]       o_dat;
 
        output  wire    [(DW/8-1):0]     o_sel;
        input                           i_ack, i_stall, i_err;
        input                           i_ack, i_stall, i_err;
 
 
        // All of our logic is really captured in the 'r_a_owner' register.
        // All of our logic is really captured in the 'r_a_owner' register.
        // This register determines who owns the bus.  If no one is requesting
        // This register determines who owns the bus.  If no one is requesting
        // the bus, ownership goes to A on the next clock.  Otherwise, if B is 
        // the bus, ownership goes to A on the next clock.  Otherwise, if B is 
        // requesting the bus and A is not, then ownership goes to not A on
        // requesting the bus and A is not, then ownership goes to not A on
        // the next clock.  (Sounds simple ...)
        // the next clock.  (Sounds simple ...)
        //
        //
        // The CYC logic is here to make certain that, by the time we determine
        // The CYC logic is here to make certain that, by the time we determine
        // who the bus owner is, we can do so based upon determined criteria.
        // who the bus owner is, we can do so based upon determined criteria.
        assign o_cyc_a = (~i_rst)&&((r_a_owner) ? i_a_cyc_a : i_b_cyc_a);
        assign o_cyc_a = ((r_a_owner) ? i_a_cyc_a : i_b_cyc_a);
        assign o_cyc_b = (~i_rst)&&((r_a_owner) ? i_a_cyc_b : i_b_cyc_b);
        assign o_cyc_b = ((r_a_owner) ? i_a_cyc_b : i_b_cyc_b);
        reg     r_a_owner;
        reg     r_a_owner;
        initial r_a_owner = 1'b1;
        initial r_a_owner = 1'b1;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_a_owner <= 1'b1;
                        r_a_owner <= 1'b1;
                else if ((~o_cyc_a)&&(~o_cyc_b))
                else if ((~o_cyc_a)&&(~o_cyc_b))
                        r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1;
                        r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1;
 
 
 
 
 
        assign o_we    = (r_a_owner) ? i_a_we    : i_b_we;
 
`ifdef  ZERO_ON_IDLE
 
        //
 
        // ZERO_ON_IDLE uses more logic than the alternative.  It should be
 
        // useful for reducing power, as these circuits tend to drive wires
 
        // all the way across the design, but it may also slow down the master
 
        // clock.  I've used it as an option when using VERILATOR, 'cause
 
        // zeroing things on idle can make them stand out all the more when
 
        // staring at wires and dumps and such.
 
        //
 
        wire    o_cyc, o_stb;
 
        assign  o_cyc = ((o_cyc_a)||(o_cyc_b));
 
        assign  o_stb = (o_cyc)&&((o_stb_a)||(o_stb_b));
 
        assign o_stb_a = (r_a_owner) ? (i_a_stb_a)&&(o_cyc_a) : (i_b_stb_a)&&(o_cyc_a);
 
        assign o_stb_b = (r_a_owner) ? (i_a_stb_b)&&(o_cyc_b) : (i_b_stb_b)&&(o_cyc_b);
 
        assign o_adr   = ((o_stb_a)|(o_stb_b))?((r_a_owner) ? i_a_adr   : i_b_adr):0;
 
        assign o_dat   = (o_stb)?((r_a_owner) ? i_a_dat   : i_b_dat):0;
 
        assign o_sel   = (o_stb)?((r_a_owner) ? i_a_sel   : i_b_sel):0;
 
        assign o_a_ack   = (o_cyc)&&( r_a_owner) ? i_ack   : 1'b0;
 
        assign o_b_ack   = (o_cyc)&&(~r_a_owner) ? i_ack   : 1'b0;
 
        assign  o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1;
 
        assign  o_b_stall = (o_cyc)&&(~r_a_owner) ? i_stall : 1'b1;
 
        assign  o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0;
 
        assign  o_b_err = (o_cyc)&&(~r_a_owner) ? i_err : 1'b0;
 
`else
        // Realistically, if neither master owns the bus, the output is a
        // Realistically, if neither master owns the bus, the output is a
        // don't care.  Thus we trigger off whether or not 'A' owns the bus.
        // don't care.  Thus we trigger off whether or not 'A' owns the bus.
        // If 'B' owns it all we care is that 'A' does not.  Likewise, if 
        // If 'B' owns it all we care is that 'A' does not.  Likewise, if 
        // neither owns the bus than the values on these various lines are
        // neither owns the bus than the values on these various lines are
        // irrelevant.
        // irrelevant.
        assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a;
        assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a;
        assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b;
        assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b;
        assign o_we    = (r_a_owner) ? i_a_we    : i_b_we;
        assign o_we    = (r_a_owner) ? i_a_we    : i_b_we;
        assign o_adr   = (r_a_owner) ? i_a_adr   : i_b_adr;
        assign o_adr   = (r_a_owner) ? i_a_adr   : i_b_adr;
        assign o_dat   = (r_a_owner) ? i_a_dat   : i_b_dat;
        assign o_dat   = (r_a_owner) ? i_a_dat   : i_b_dat;
 
        assign o_sel   = (r_a_owner) ? i_a_sel   : i_b_sel;
 
 
        // We cannot allow the return acknowledgement to ever go high if
        // We cannot allow the return acknowledgement to ever go high if
        // the master in question does not own the bus.  Hence we force it
        // the master in question does not own the bus.  Hence we force it
        // low if the particular master doesn't own the bus.
        // low if the particular master doesn't own the bus.
        assign  o_a_ack   = ( r_a_owner) ? i_ack   : 1'b0;
        assign  o_a_ack   = ( r_a_owner) ? i_ack   : 1'b0;
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        // These error lines will be implemented soon, as soon as the rest of
        // These error lines will be implemented soon, as soon as the rest of
        // the Zip CPU is ready to support them.
        // the Zip CPU is ready to support them.
        //
        //
        assign  o_a_err = ( r_a_owner) ? i_err : 1'b0;
        assign  o_a_err = ( r_a_owner) ? i_err : 1'b0;
        assign  o_b_err = (~r_a_owner) ? i_err : 1'b0;
        assign  o_b_err = (~r_a_owner) ? i_err : 1'b0;
 
`endif
 
 
endmodule
endmodule
 
 
 
 
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