| Line 61... |
Line 61... |
// Bit reversal pre-logic
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// Bit reversal pre-logic
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wire [31:0] w_brev_result;
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wire [31:0] w_brev_result;
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genvar k;
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genvar k;
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generate
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generate
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for(k=0; k<32; k=k+1)
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for(k=0; k<32; k=k+1)
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begin : bit_reversal_cpuop
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assign w_brev_result[k] = i_b[31-k];
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assign w_brev_result[k] = i_b[31-k];
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endgenerate
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end endgenerate
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// Popcount pre-logic
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// Popcount pre-logic
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wire [31:0] w_popc_result;
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wire [31:0] w_popc_result;
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assign w_popc_result[5:0]=
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assign w_popc_result[5:0]=
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({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
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({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
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| Line 131... |
Line 132... |
assign o_illegal = r_illegal;
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assign o_illegal = r_illegal;
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end else begin
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end else begin
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//
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//
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// Multiply pre-logic
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// Multiply pre-logic
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//
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//
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wire [16:0] w_mpy_a_input, w_mpy_b_input;
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wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
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wire [33:0] w_mpy_result;
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wire [33:0] w_mpy_result;
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reg [31:0] r_mpy_result;
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reg [31:0] r_mpy_result;
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assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
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assign w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
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assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
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assign w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
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