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[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Diff between revs 3 and 12
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| Rev 3 |
Rev 12 |
| Line 65... |
Line 65... |
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'ha: { c, o_c } <= i_a + i_b; // Add
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4'hb: o_c <= i_a | i_b; // Or
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4'hb: o_c <= i_a | i_b; // Or
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4'hc: o_c <= i_a ^ i_b; // Xor
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4'hc: o_c <= i_a ^ i_b; // Xor
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4'hd: { c, o_c } <= {1'b0, i_a } << i_b[4:0]; // LSL
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4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
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4'he: { c, o_c } <= { i_a[31],i_a}>> (i_b[4:0]);// ASR
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4'he: { c, o_c } <= (|i_b[31:5])? {(33){i_a[31]}}:{ i_a[31],i_a}>> (i_b[4:0]);// ASR
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4'hf: { c, o_c } <= { 1'b0, i_a } >> (i_b[4:0]);// LSR
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4'hf: { c, o_c } <= (|i_b[31:5])? 33'h00 : { 1'b0, i_a } >> (i_b[4:0]);// LSR
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default: o_c <= i_b; // MOV, LDI
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default: o_c <= i_b; // MOV, LDI
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endcase
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endcase
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end
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end
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assign z = (o_c == 32'h0000);
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assign z = (o_c == 32'h0000);
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