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[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Diff between revs 138 and 175

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Rev 138 Rev 175
Line 51... Line 51...
        assign  w_rol_tmp = { i_a, i_a } << i_b[4:0];
        assign  w_rol_tmp = { i_a, i_a } << i_b[4:0];
        wire    [31:0]   w_rol_result;
        wire    [31:0]   w_rol_result;
        assign  w_rol_result = w_rol_tmp[63:32]; // Won't set flags
        assign  w_rol_result = w_rol_tmp[63:32]; // Won't set flags
 
 
        // Shift register pre-logic
        // Shift register pre-logic
        wire    [32:0]           w_lsr_result, w_asr_result;
        wire    [32:0]           w_lsr_result, w_asr_result, w_lsl_result;
 
        wire    signed  [32:0]   w_pre_asr_input, w_pre_asr_shifted;
 
        assign  w_pre_asr_input = { i_a, 1'b0 };
 
        assign  w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
        assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
        assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
                                : ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
                                : w_pre_asr_shifted;// ASR
        assign  w_lsr_result = (|i_b[31:5])? 33'h00
        assign  w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
                                : ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
                                :((i_b[5])?{32'h0,i_a[31]}
 
 
 
                                : ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR
 
        assign  w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
 
                                :((i_b[5])?{i_a[0], 32'h0}
 
                                : ({1'b0, i_a } << i_b[4:0]));   // LSL
 
 
        // Bit reversal pre-logic
        // Bit reversal pre-logic
        wire    [31:0]   w_brev_result;
        wire    [31:0]   w_brev_result;
        genvar  k;
        genvar  k;
        generate
        generate
Line 114... Line 122...
                        4'b0001:   o_c   <= i_a & i_b;          // BTST/And
                        4'b0001:   o_c   <= i_a & i_b;          // BTST/And
                        4'b0010:{c,o_c } <= i_a + i_b;          // Add
                        4'b0010:{c,o_c } <= i_a + i_b;          // Add
                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
                        4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
`ifndef LONG_MPY
`ifndef LONG_MPY
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
`endif
`endif
                        4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
Line 294... Line 302...
                        4'b0001:   o_c   <= i_a & i_b;          // BTST/And
                        4'b0001:   o_c   <= i_a & i_b;          // BTST/And
                        4'b0010:{c,o_c } <= i_a + i_b;          // Add
                        4'b0010:{c,o_c } <= i_a + i_b;          // Add
                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
                        4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
`ifdef  LONG_MPY
`ifdef  LONG_MPY
                        4'b1000:   o_c   <= r_mpy_result[31:0]; // MPY
                        4'b1000:   o_c   <= r_mpy_result[31:0]; // MPY
`else
`else
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI

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