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// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
Line 30... Line 30...
//              http://www.gnu.org/licenses/gpl.html
//              http://www.gnu.org/licenses/gpl.html
//
//
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
`define LONG_MPY
`include "cpudefs.v"
module  cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
//
                        o_illegal, o_busy);
module  cpuops(i_clk,i_rst, i_ce, i_op, i_a, i_b, o_c, o_f, o_valid,
        parameter       IMPLEMENT_MPY = 1;
                        o_busy);
 
        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
        input           i_clk, i_rst, i_ce;
        input           i_clk, i_rst, i_ce;
        input           [3:0]    i_op;
        input           [3:0]    i_op;
        input           [31:0]   i_a, i_b;
        input           [31:0]   i_a, i_b;
        input                   i_valid;
 
        output  reg     [31:0]   o_c;
        output  reg     [31:0]   o_c;
        output  wire    [3:0]    o_f;
        output  wire    [3:0]    o_f;
        output  reg             o_valid;
        output  reg             o_valid;
        output  wire            o_illegal;
 
        output  wire            o_busy;
        output  wire            o_busy;
 
 
        // Rotate-left pre-logic
        // Rotate-left pre-logic
        wire    [63:0]   w_rol_tmp;
        wire    [63:0]   w_rol_tmp;
        assign  w_rol_tmp = { i_a, i_a } << i_b[4:0];
        assign  w_rol_tmp = { i_a, i_a } << i_b[4:0];
Line 97... Line 96...
                        set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
                        set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
                                ||(i_op == 4'h6) // LSL
                                ||(i_op == 4'h6) // LSL
                                ||(i_op == 4'h5)); // LSR
                                ||(i_op == 4'h5)); // LSR
 
 
`ifdef  LONG_MPY
        wire    [63:0]   mpy_result; // Where we dump the multiply result
        reg     mpyhi;
        reg     mpyhi;          // Return the high half of the multiply
        wire    mpybusy;
        wire    mpybusy;        // The multiply is busy if true
`endif
        wire    mpydone;        // True if we'll be valid on the next clock;
 
 
        // A 4-way multiplexer can be done in one 6-LUT.
        // A 4-way multiplexer can be done in one 6-LUT.
        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
        //      the Xilinx multiplexer fabric that follows. 
        //      the Xilinx multiplexer fabric that follows. 
        // Given that we wish to apply this multiplexer approach to 33-bits,
        // Given that we wish to apply this multiplexer approach to 33-bits,
        // this will cost a minimum of 132 6-LUTs.
        // this will cost a minimum of 132 6-LUTs.
 
 
 
        wire    this_is_a_multiply_op;
 
        assign  this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8));
 
 
        generate
        generate
        if (IMPLEMENT_MPY == 0)
        if (IMPLEMENT_MPY == 0)
        begin
        begin // No multiply support.
 
                assign  mpy_result = 63'h00;
 
        end else if (IMPLEMENT_MPY == 1)
 
        begin // Our single clock option (no extra clocks)
 
                wire    signed  [63:0]   w_mpy_a_input, w_mpy_b_input;
 
                assign  w_mpy_a_input = {{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
 
                assign  w_mpy_b_input = {{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
 
                assign  mpy_result = w_mpy_a_input * w_mpy_b_input;
 
                assign  mpybusy = 1'b0;
 
                assign  mpydone = 1'b0;
 
                always @(*) mpyhi = 1'b0; // Not needed
 
        end else if (IMPLEMENT_MPY == 2)
 
        begin // Our two clock option (ALU must pause for 1 clock)
 
                reg     signed  [63:0]   r_mpy_a_input, r_mpy_b_input;
                always @(posedge i_clk)
                always @(posedge i_clk)
                if (i_ce)
 
                begin
                begin
                        pre_sign <= (i_a[31]);
                        r_mpy_a_input <={{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
                        c <= 1'b0;
                        r_mpy_b_input <={{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
                        casez(i_op)
 
                        4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
 
                        4'b0001:   o_c   <= i_a & i_b;          // BTST/And
 
                        4'b0010:{c,o_c } <= i_a + i_b;          // Add
 
                        4'b0011:   o_c   <= i_a | i_b;          // Or
 
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
 
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
 
                        4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
 
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
 
`ifndef LONG_MPY
 
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
 
`endif
 
                        4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
 
                        // 4'h1010: The unimplemented MPYU,
 
                        // 4'h1011: and here for the unimplemented MPYS
 
                        4'b1100:   o_c   <= w_brev_result;      // BREV
 
                        4'b1101:   o_c   <= w_popc_result;      // POPC
 
                        4'b1110:   o_c   <= w_rol_result;       // ROL
 
                        default:   o_c   <= i_b;                // MOV, LDI
 
                        endcase
 
                end
                end
 
 
                assign o_busy = 1'b0;
                assign  mpy_result = r_mpy_a_input * r_mpy_b_input;
 
                assign  mpybusy = 1'b0;
 
 
                reg     r_illegal;
 
                always @(posedge i_clk)
 
                        r_illegal <= (i_ce)&&((i_op == 4'ha)||(i_op == 4'hb)
 
`ifdef  LONG_MPY
 
                                ||(i_op == 4'h8)
 
`endif
 
                        );
 
                assign o_illegal = r_illegal;
 
        end else begin
 
                //
 
                // Multiply pre-logic
 
                //
 
`ifdef  LONG_MPY
 
                reg     [63:0]   r_mpy_result;
 
                if (IMPLEMENT_MPY == 1)
 
                begin // Our two clock option (one clock extra)
 
                        reg     signed  [64:0]   r_mpy_a_input, r_mpy_b_input;
 
                        reg                     mpypipe, x;
 
                        initial mpypipe = 1'b0;
                        initial mpypipe = 1'b0;
 
                reg     mpypipe;
                        always @(posedge i_clk)
                        always @(posedge i_clk)
                                mpypipe <= (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8));
                        if (i_rst)
 
                                mpypipe <= 1'b0;
 
                        else
 
                                mpypipe <= (this_is_a_multiply_op);
 
 
 
                assign  mpydone = mpypipe; // this_is_a_multiply_op;
 
                always @(posedge i_clk)
 
                        if (this_is_a_multiply_op)
 
                                mpyhi  = i_op[1];
 
        end else if (IMPLEMENT_MPY == 3)
 
        begin // Our three clock option (ALU pauses for 2 clocks)
 
                reg     signed  [63:0]   r_smpy_result;
 
                reg             [63:0]   r_umpy_result;
 
                reg     signed  [31:0]   r_mpy_a_input, r_mpy_b_input;
 
                reg             [1:0]    mpypipe;
 
                reg             [1:0]    r_sgn;
 
 
 
                initial mpypipe = 2'b0;
 
                always @(posedge i_clk)
 
                        if (i_rst)
 
                                mpypipe <= 2'b0;
 
                        else
 
                        mpypipe <= { mpypipe[0], this_is_a_multiply_op };
 
 
 
                // First clock
                        always @(posedge i_clk)
                        always @(posedge i_clk)
                        if (i_ce)
 
                        begin
                        begin
                                r_mpy_a_input <= {{(33){(i_a[31])&(i_op[0])}},
                        r_mpy_a_input <= i_a[31:0];
                                                        i_a[31:0]};
                        r_mpy_b_input <= i_b[31:0];
                                r_mpy_b_input <= {{(33){(i_b[31])&(i_op[0])}},
                        r_sgn <= { r_sgn[0], i_op[0] };
                                                        i_b[31:0]};
 
                        end
                        end
 
 
 
                // Second clock
 
`ifdef  VERILATOR
 
                wire    signed  [63:0]   s_mpy_a_input, s_mpy_b_input;
 
                wire            [63:0]   u_mpy_a_input, u_mpy_b_input;
 
 
 
                assign  s_mpy_a_input = {{(32){r_mpy_a_input[31]}},r_mpy_a_input};
 
                assign  s_mpy_b_input = {{(32){r_mpy_b_input[31]}},r_mpy_b_input};
 
                assign  u_mpy_a_input = {32'h00,r_mpy_a_input};
 
                assign  u_mpy_b_input = {32'h00,r_mpy_b_input};
                        always @(posedge i_clk)
                        always @(posedge i_clk)
                                if (mpypipe)
                        r_smpy_result = s_mpy_a_input * s_mpy_b_input;
                                        {x, r_mpy_result} = r_mpy_a_input
 
                                                        * r_mpy_b_input;
 
                        always @(posedge i_clk)
                        always @(posedge i_clk)
                                if (i_ce)
                        r_umpy_result = u_mpy_a_input * u_mpy_b_input;
 
`else
 
 
 
                wire            [31:0]   u_mpy_a_input, u_mpy_b_input;
 
 
 
                assign  u_mpy_a_input = r_mpy_a_input;
 
                assign  u_mpy_b_input = r_mpy_b_input;
 
 
 
                always @(posedge i_clk)
 
                        r_smpy_result = r_mpy_a_input * r_mpy_b_input;
 
                always @(posedge i_clk)
 
                        r_umpy_result = u_mpy_a_input * u_mpy_b_input;
 
`endif
 
 
 
                always @(posedge i_clk)
 
                        if (this_is_a_multiply_op)
                                        mpyhi  = i_op[1];
                                        mpyhi  = i_op[1];
                        assign  mpybusy = mpypipe;
                assign  mpybusy = mpypipe[0];
                end else if (IMPLEMENT_MPY == 2)
                assign  mpy_result = (r_sgn[1])?r_smpy_result:r_umpy_result;
 
                assign  mpydone = mpypipe[1];
 
 
 
                // Results are then set on the third clock
 
        end else // if (IMPLEMENT_MPY <= 4)
                begin // The three clock option
                begin // The three clock option
 
                reg     [63:0]   r_mpy_result;
                        reg     [31:0]   r_mpy_a_input, r_mpy_b_input;
                        reg     [31:0]   r_mpy_a_input, r_mpy_b_input;
                        reg             r_mpy_signed;
                        reg             r_mpy_signed;
                        reg     [1:0]    mpypipe;
                reg     [2:0]    mpypipe;
 
 
                        // First clock, latch in the inputs
                        // First clock, latch in the inputs
                        always @(posedge i_clk)
                        always @(posedge i_clk)
                        begin
                        begin
                                // mpypipe indicates we have a multiply in the
                                // mpypipe indicates we have a multiply in the
                                // pipeline.  In this case, the multiply
                                // pipeline.  In this case, the multiply
                                // pipeline is a two stage pipeline, so we need 
                                // pipeline is a two stage pipeline, so we need 
                                // two bits in the pipe.
                                // two bits in the pipe.
                                mpypipe[0] <= (i_ce)&&((i_op[3:1]==3'h5)
                        if (i_rst)
                                                        ||(i_op[3:0]==4'h8));
                                mpypipe <= 3'h0;
 
                        else begin
 
                                mpypipe[0] <= this_is_a_multiply_op;
                                mpypipe[1] <= mpypipe[0];
                                mpypipe[1] <= mpypipe[0];
 
                                mpypipe[2] <= mpypipe[1];
 
                        end
 
 
                                if (i_op[0]) // i.e. if signed multiply
                                if (i_op[0]) // i.e. if signed multiply
                                begin
                                begin
                                        r_mpy_a_input <= {(~i_a[31]),i_a[30:0]};
                                        r_mpy_a_input <= {(~i_a[31]),i_a[30:0]};
                                        r_mpy_b_input <= {(~i_b[31]),i_b[30:0]};
                                        r_mpy_b_input <= {(~i_b[31]),i_b[30:0]};
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                                // case of 64 bit multiply.  We'll keep track
                                // case of 64 bit multiply.  We'll keep track
                                // of it, though, and pretend in all other
                                // of it, though, and pretend in all other
                                // cases.
                                // cases.
                                r_mpy_signed  <= i_op[0];
                                r_mpy_signed  <= i_op[0];
 
 
                                if (i_ce)
                        if (this_is_a_multiply_op)
                                        mpyhi  = i_op[1];
                                        mpyhi  = i_op[1];
                        end
                        end
 
 
                        assign  mpybusy = |mpypipe;
                assign  mpybusy = |mpypipe[1:0];
 
                assign  mpydone = mpypipe[2];
 
 
                        // Second clock, do the multiplies, get the "partial
                        // Second clock, do the multiplies, get the "partial
                        // products".  Here, we break our input up into two
                        // products".  Here, we break our input up into two
                        // halves, 
                        // halves, 
                        //
                        //
Line 274... Line 308...
                                        { 32'h00, pp_l[31:16] }
                                        { 32'h00, pp_l[31:16] }
                                        + { 15'h00, pp_oi }
                                        + { 15'h00, pp_oi }
                                        + { pp_s, 15'h00 }
                                        + { pp_s, 15'h00 }
                                        + { pp_f, 16'h00 };
                                        + { pp_f, 16'h00 };
                        end
                        end
                end // Fourth clock -- results are available for writeback.
 
`else
                assign  mpy_result = r_mpy_result;
                wire    signed  [16:0]   w_mpy_a_input, w_mpy_b_input;
                // Fourth clock -- results are clocked into writeback
                wire            [33:0]   w_mpy_result;
        end
                reg             [31:0]   r_mpy_result;
        endgenerate // All possible multiply results have been determined
                assign  w_mpy_a_input ={ ((i_a[15])&(i_op[0])), i_a[15:0] };
 
                assign  w_mpy_b_input ={ ((i_b[15])&(i_op[0])), i_b[15:0] };
 
                assign  w_mpy_result   = w_mpy_a_input * w_mpy_b_input;
 
                always @(posedge i_clk)
 
                        if (i_ce)
 
                                r_mpy_result  = w_mpy_result[31:0];
 
`endif
 
 
 
                //
                //
                // The master ALU case statement
                // The master ALU case statement
                //
                //
                always @(posedge i_clk)
                always @(posedge i_clk)
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                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
                        4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
`ifdef  LONG_MPY
                4'b1000:   o_c   <= mpy_result[31:0]; // MPY
                        4'b1000:   o_c   <= r_mpy_result[31:0]; // MPY
 
`else
 
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
 
`endif
 
                        4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
`ifdef  LONG_MPY
                4'b1010:   o_c   <= mpy_result[63:32]; // MPYHU
                        4'b1010:   o_c   <= r_mpy_result[63:32]; // MPYHU
                4'b1011:   o_c   <= mpy_result[63:32]; // MPYHS
                        4'b1011:   o_c   <= r_mpy_result[63:32]; // MPYHS
 
`else
 
                        4'b1010:   o_c   <= r_mpy_result; // MPYU
 
                        4'b1011:   o_c   <= r_mpy_result; // MPYS
 
`endif
 
                        4'b1100:   o_c   <= w_brev_result;      // BREV
                        4'b1100:   o_c   <= w_brev_result;      // BREV
                        4'b1101:   o_c   <= w_popc_result;      // POPC
                        4'b1101:   o_c   <= w_popc_result;      // POPC
                        4'b1110:   o_c   <= w_rol_result;       // ROL
                        4'b1110:   o_c   <= w_rol_result;       // ROL
                        default:   o_c   <= i_b;                // MOV, LDI
                        default:   o_c   <= i_b;                // MOV, LDI
                        endcase
                        endcase
                end else if (r_busy)
        end else // if (mpydone)
`ifdef  LONG_MPY
                o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
                        o_c <= (mpyhi)?r_mpy_result[63:32]:r_mpy_result[31:0];
 
`else
 
                        o_c <= r_mpy_result;
 
`endif
 
 
 
                reg     r_busy;
                reg     r_busy;
                initial r_busy = 1'b0;
                initial r_busy = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        r_busy <= (~i_rst)&&(i_ce)&&(i_valid)
                if (i_rst)
`ifdef  LONG_MPY
                        r_busy <= 1'b0;
                                        &&((i_op[3:1] == 3'h5)
                else
                                                ||(i_op[3:0] == 4'h8))||mpybusy;
                        r_busy <= ((IMPLEMENT_MPY > 1)
`else
                                        &&(this_is_a_multiply_op))||mpybusy;
                                        &&(i_op[3:1] == 3'h5);
        assign  o_busy = (r_busy); // ||((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op));
`endif
 
 
 
                assign o_busy = r_busy;
 
 
 
                assign o_illegal = 1'b0;
 
        end endgenerate
 
 
 
        assign  z = (o_c == 32'h0000);
        assign  z = (o_c == 32'h0000);
        assign  n = (o_c[31]);
        assign  n = (o_c[31]);
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
 
 
Line 355... Line 364...
 
 
        initial o_valid = 1'b0;
        initial o_valid = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        o_valid <= 1'b0;
                        o_valid <= 1'b0;
 
                else if (IMPLEMENT_MPY <= 1)
 
                        o_valid <= (i_ce);
                else
                else
                        o_valid <= (i_ce)&&(i_valid)
                        o_valid <=((i_ce)&&(!this_is_a_multiply_op))||(mpydone);
`ifdef  LONG_MPY
 
                                &&(i_op[3:1] != 3'h5)&&(i_op[3:0] != 4'h8)
 
                                ||(o_busy)&&(~mpybusy);
 
`else
 
                                &&(i_op[3:1] != 3'h5)||(o_busy);
 
`endif
 
endmodule
endmodule
 
 
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