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[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Diff between revs 201 and 205

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Line 126... Line 126...
                end
                end
 
 
                assign  mpy_result = r_mpy_a_input * r_mpy_b_input;
                assign  mpy_result = r_mpy_a_input * r_mpy_b_input;
                assign  mpybusy = 1'b0;
                assign  mpybusy = 1'b0;
 
 
                initial mpypipe = 1'b0;
 
                reg     mpypipe;
                reg     mpypipe;
 
                initial mpypipe = 1'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                        if (i_rst)
                        if (i_rst)
                                mpypipe <= 1'b0;
                                mpypipe <= 1'b0;
                        else
                        else
                                mpypipe <= (this_is_a_multiply_op);
                                mpypipe <= (this_is_a_multiply_op);
Line 203... Line 203...
                reg     [31:0]   r_mpy_a_input, r_mpy_b_input;
                reg     [31:0]   r_mpy_a_input, r_mpy_b_input;
                reg             r_mpy_signed;
                reg             r_mpy_signed;
                reg     [2:0]    mpypipe;
                reg     [2:0]    mpypipe;
 
 
                // First clock, latch in the inputs
                // First clock, latch in the inputs
 
                initial mpypipe = 3'b0;
                always @(posedge i_clk)
                always @(posedge i_clk)
                begin
                begin
                        // mpypipe indicates we have a multiply in the
                        // mpypipe indicates we have a multiply in the
                        // pipeline.  In this case, the multiply
                        // pipeline.  In this case, the multiply
                        // pipeline is a two stage pipeline, so we need 
                        // pipeline is a two stage pipeline, so we need 

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