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[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Diff between revs 2 and 3

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Rev 2 Rev 3
Line 55... Line 55...
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_ce)
                if (i_ce)
                begin
                begin
                        pre_sign <= (i_a[31]);
                        pre_sign <= (i_a[31]);
                        c <= 1'b0;
                        c <= 1'b0;
                        case(i_op)
                        casez(i_op)
                        4'h0: { c, o_c } <= {(i_b>i_a),i_a - i_b};// CMP (SUB)
                        4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
                        4'h1:      o_c   <= i_a & i_b;          // BTST (And)
                        4'b?001:   o_c   <= i_a & i_b;          // BTST/And
                        4'h2:      o_c   <=       i_b;          // MOV
 
                        // 4'h3:   o_c   <= { i_b[15:0],i_a[15:6],6'h20};//TRAP
 
                        // 4'h4:   o_c   <= i_a[15:0] * i_b[15:0];
                        // 4'h4:   o_c   <= i_a[15:0] * i_b[15:0];
                        4'h5:      o_c   <= w_rol_result;       // ROL
                        4'h5:      o_c   <= w_rol_result;       // ROL
                        4'h6:      o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        4'h6:      o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        4'h7:      o_c   <= { i_b[15:0], i_a[15:0] }; // LODIHI
                        4'h7:      o_c   <= { i_b[15:0], i_a[15:0] }; // LODIHI
                        4'h8: { c, o_c } <= {(i_b>i_a), i_a - i_b };    // Sub
 
                        4'h9:      o_c   <= i_a & i_b;          // And
 
                        4'ha: { c, o_c } <= i_a + i_b;          // Add
                        4'ha: { c, o_c } <= i_a + i_b;          // Add
                        4'hb:      o_c   <= i_a | i_b;          // Or
                        4'hb:      o_c   <= i_a | i_b;          // Or
                        4'hc:      o_c   <= i_a ^ i_b;          // Xor
                        4'hc:      o_c   <= i_a ^ i_b;          // Xor
                        4'hd: { c, o_c } <= {1'b0, i_a } << i_b[4:0];    // LSL
                        4'hd: { c, o_c } <= {1'b0, i_a } << i_b[4:0];    // LSL
                        4'he: { c, o_c } <= { i_a[31],i_a}>> (i_b[4:0]);// ASR
                        4'he: { c, o_c } <= { i_a[31],i_a}>> (i_b[4:0]);// ASR

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