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[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Diff between revs 62 and 69

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//
//
// Filename:    cpuops.v
// Filename:    cpuops.v
//
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
//
// Purpose:     
// Purpose:     This supports the instruction set reordering of operations
 
//              created by the second generation instruction set, as well as
 
//      the new operations of POPC (population count) and BREV (bit reversal).
 
//
//
//
// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015, Gisselquist Technology, LLC
//
//
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        assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
        assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
                                : ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
                                : ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
        assign  w_lsr_result = (|i_b[31:5])? 33'h00
        assign  w_lsr_result = (|i_b[31:5])? 33'h00
                                : ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
                                : ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
 
 
 
        // Bit reversal pre-logic
 
        wire    [31:0]   w_brev_result;
 
        genvar  k;
 
        generate
 
        for(k=0; k<32; k=k+1)
 
                assign w_brev_result[k] = i_b[31-k];
 
        endgenerate
 
 
 
        // Popcount pre-logic
 
        wire    [31:0]   w_popc_result;
 
        assign  w_popc_result[5:0]=
 
                 ({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
 
                +({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
 
                +({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
 
                +({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
 
                +({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
 
                +({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
 
                +({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
 
                +({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
 
        assign  w_popc_result[31:6] = 26'h00;
 
 
 
        // Prelogic for our flags registers
        wire    z, n, v;
        wire    z, n, v;
        reg     c, pre_sign, set_ovfl;
        reg     c, pre_sign, set_ovfl;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_ce)
                if (i_ce) // 1 LUT
                        set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
                        set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
                                                &&(i_a[31] != i_b[31]))
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
                                ||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
                                ||(i_op == 4'h6) // LSL
                                ||(i_op == 4'hd) // LSL
                                ||(i_op == 4'h5)); // LSR
                                ||(i_op == 4'hf)); // LSR
 
 
 
 
 
        // A 4-way multiplexer can be done in one 6-LUT.
        // A 4-way multiplexer can be done in one 6-LUT.
        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
        //      the Xilinx multiplexer fabric that follows. 
        //      the Xilinx multiplexer fabric that follows. 
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                if (i_ce)
                if (i_ce)
                begin
                begin
                        pre_sign <= (i_a[31]);
                        pre_sign <= (i_a[31]);
                        c <= 1'b0;
                        c <= 1'b0;
                        casez(i_op)
                        casez(i_op)
                        4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
                        4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
                        4'b?001:   o_c   <= i_a & i_b;          // BTST/And
                        4'b0001:   o_c   <= i_a & i_b;          // BTST/And
                        // 4'h3: There's a hole here for the unimplemented MPYU,
                        4'b0010:{c,o_c } <= i_a + i_b;          // Add
                        // 4'h4: and here for the unimplemented MPYS
                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'h5:      o_c   <= w_rol_result;       // ROL
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'h6:      o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'h7:      o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
                        4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
                        4'ha: { c, o_c } <= i_a + i_b;          // Add
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                        4'hb:      o_c   <= i_a | i_b;          // Or
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
                        4'hc:      o_c   <= i_a ^ i_b;          // Xor
                        4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
                        // 4'h1010: The unimplemented MPYU,
                        4'he: { o_c, c } <= w_asr_result[32:0];  // ASR
                        // 4'h1011: and here for the unimplemented MPYS
                        4'hf: { o_c, c } <= w_lsr_result[32:0];  // LSR
                        4'b1100:   o_c   <= w_brev_result;      // BREV
 
                        4'b1101:   o_c   <= w_popc_result;      // POPC
 
                        4'b1110:   o_c   <= w_rol_result;       // ROL
                        default:   o_c   <=       i_b;          // MOV, LDI
                        default:   o_c   <=       i_b;          // MOV, LDI
                        endcase
                        endcase
                end
                end
        end else begin
        end else begin
                //
                //
                // Multiply pre-logic
                // Multiply pre-logic
                //
                //
 
                wire    signed_mpy;
 
                assign  signed_mpy = i_op[0];
                wire    signed  [16:0]   w_mpy_a_input, w_mpy_b_input;
                wire    signed  [16:0]   w_mpy_a_input, w_mpy_b_input;
                wire    signed  [33:0]   w_mpy_result;
                wire    signed  [33:0]   w_mpy_result;
                assign  w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
                assign  w_mpy_a_input ={ ((i_a[15])&&(signed_mpy)), i_a[15:0] };
                assign  w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
                assign  w_mpy_b_input ={ ((i_b[15])&&(signed_mpy)), i_b[15:0] };
                assign  w_mpy_result  = w_mpy_a_input * w_mpy_b_input;
                assign  w_mpy_result  = w_mpy_a_input * w_mpy_b_input;
 
 
 
 
                //
                //
                // The master ALU case statement
                // The master ALU case statement
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                if (i_ce)
                if (i_ce)
                begin
                begin
                        pre_sign <= (i_a[31]);
                        pre_sign <= (i_a[31]);
                        c <= 1'b0;
                        c <= 1'b0;
                        casez(i_op)
                        casez(i_op)
                        4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
                        4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
                        4'b?001:   o_c   <= i_a & i_b;          // BTST/And
                        4'b0001:   o_c   <= i_a & i_b;          // BTST/And
                        4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU
                        4'b0010:{c,o_c } <= i_a + i_b;          // Add
                        4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS
                        4'b0011:   o_c   <= i_a | i_b;          // Or
                        4'h5:      o_c   <= w_rol_result;       // ROL
                        4'b0100:   o_c   <= i_a ^ i_b;          // Xor
                        4'h6:      o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
                        4'h7:      o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
                        4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
                        4'ha: { c, o_c } <= i_a + i_b;          // Add
                        4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
                        4'hb:      o_c   <= i_a | i_b;          // Or
                        4'b1000:   o_c   <= { i_b[15: 0], i_a[15:0] }; // LODIHI
                        4'hc:      o_c   <= i_a ^ i_b;          // Xor
                        4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
                        4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
                        4'b1010:{c,o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU
                        4'he: { o_c, c } <= w_asr_result[32:0];  // ASR
                        4'b1011:{c,o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS
                        4'hf: { o_c, c } <= w_lsr_result[32:0];  // LSR
                        4'b1100:   o_c   <= w_brev_result;      // BREV
 
                        4'b1101:   o_c   <= w_popc_result;      // POPC
 
                        4'b1110:   o_c   <= w_rol_result;       // ROL
                        default:   o_c   <=       i_b;          // MOV, LDI
                        default:   o_c   <=       i_b;          // MOV, LDI
                        endcase
                        endcase
                end
                end
        end endgenerate
        end endgenerate
 
 

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