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[/] [zipcpu/] [trunk/] [rtl/] [core/] [div.v] - Diff between revs 88 and 160

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// Creator:     Dan Gisselquist, Ph.D.
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//              Gisselquist Technology, LLC
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
//
// Copyright (C) 2015, Gisselquist Technology, LLC
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
//
// This program is free software (firmware): you can redistribute it and/or
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
// your option) any later version.
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        // Output parameters
        // Output parameters
        output  reg             o_busy, o_valid, o_err;
        output  reg             o_busy, o_valid, o_err;
        output  reg [(BW-1):0]   o_quotient;
        output  reg [(BW-1):0]   o_quotient;
        output  wire    [3:0]    o_flags;
        output  wire    [3:0]    o_flags;
 
 
 
        // r_busy is an internal busy register.  It will clear one clock
 
        // before we are valid, so it can't be o_busy ...
 
        //
 
        reg                     r_busy;
        reg     [(2*BW-2):0]     r_divisor;
        reg     [(2*BW-2):0]     r_divisor;
        reg     [(BW-1):0]       r_dividend;
        reg     [(BW-1):0]       r_dividend;
        wire    [(BW):0] diff; // , xdiff[(BW-1):0];
        wire    [(BW):0] diff; // , xdiff[(BW-1):0];
        assign  diff = r_dividend - r_divisor[(BW-1):0];
        assign  diff = r_dividend - r_divisor[(BW-1):0];
        // assign       xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
        // assign       xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
 
 
        reg             r_sign, pre_sign, r_z, r_c;
        reg             r_sign, pre_sign, r_z, r_c, last_bit;
        reg     [(LGBW):0]       r_bit;
        reg     [(LGBW-1):0]     r_bit;
 
 
 
        initial r_busy = 1'b0;
 
        always @(posedge i_clk)
 
                if (i_rst)
 
                        r_busy <= 1'b0;
 
                else if (i_wr)
 
                        r_busy <= 1'b1;
 
                else if ((last_bit)||(o_err))
 
                        r_busy <= 1'b0;
 
 
 
        initial o_busy = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                begin
 
                        o_busy <= 1'b0;
                        o_busy <= 1'b0;
                end else if (i_wr)
                else if (i_wr)
                begin
 
                        o_busy <= 1'b1;
                        o_busy <= 1'b1;
                end else if ((o_busy)&&((r_bit == 6'h0)||(o_err)))
                else if (((last_bit)||(o_err))&&(~r_sign))
 
                        o_busy <= 1'b0;
 
                else if (~r_busy)
                        o_busy <= 1'b0;
                        o_busy <= 1'b0;
                // else busy is zero and stays at zero
 
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_wr))
                if ((i_rst)||(i_wr))
                        o_valid <= 1'b0;
                        o_valid <= 1'b0;
                else if (o_busy)
                else if (r_busy)
                begin
                begin
                        if ((r_bit == 6'h0)||(o_err))
                        if ((last_bit)||(o_err))
                                o_valid <= (o_err)||(~r_sign);
                                o_valid <= (o_err)||(~r_sign);
                end else if (r_sign)
                end else if (r_sign)
                begin
                begin
                        // if (o_err), o_valid is already one.
                        // if (o_err), o_valid is already one.
                        //      if not, o_valid has not yet become one.
                        //      if not, o_valid has not yet become one.
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                if((i_rst)||(o_valid))
                if((i_rst)||(o_valid))
                        o_err <= 1'b0;
                        o_err <= 1'b0;
                else if (o_busy)
                else if (o_busy)
                        o_err <= (r_divisor == 0);
                        o_err <= (r_divisor == 0);
 
 
 
        initial last_bit = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
 
                if ((i_wr)||(pre_sign)||(i_rst))
 
                        last_bit <= 1'b0;
 
                else if (r_busy)
 
                        last_bit <= (r_bit == {{(LGBW-1){1'b0}},1'b1});
 
 
 
        always @(posedge i_clk)
 
                // if (i_rst) r_busy <= 1'b0;
 
                // else
                if (i_wr)
                if (i_wr)
                begin
                begin
 
                        //
 
                        // Set our values upon an initial command.  Here's
 
                        // where we come in and start.
 
                        //
 
                        // r_busy <= 1'b1;
 
                        //
                        o_quotient <= 0;
                        o_quotient <= 0;
                        // r_bit <= { 1'b1, {(LGBW){1'b0}} };
                        r_bit <= {(LGBW){1'b1}};
                        r_bit <= { 1'b0, {(LGBW){1'b1}} };
 
                        r_divisor <= {  i_denominator, {(BW-1){1'b0}} };
                        r_divisor <= {  i_denominator, {(BW-1){1'b0}} };
                        r_dividend <=  i_numerator;
                        r_dividend <=  i_numerator;
                        r_sign <= 1'b0;
                        r_sign <= 1'b0;
                        pre_sign <= i_signed;
                        pre_sign <= i_signed;
                        r_z <= 1'b1;
                        r_z <= 1'b1;
                end else if (pre_sign)
                end else if (pre_sign)
                begin
                begin
                        // r_bit <= r_bit - 1;
                        //
                        r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));;
                        // Note that we only come in here, for one clock, if
 
                        // our initial value may have been signed.  If we are
 
                        // doing an unsigned divide, we then skip this step.
 
                        //
 
                        r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));
 
                        // Negate our dividend if necessary so that it becomes
 
                        // a magnitude only value
                        if (r_dividend[BW-1])
                        if (r_dividend[BW-1])
                                r_dividend <= -r_dividend;
                                r_dividend <= -r_dividend;
 
                        // Do the same with the divisor--rendering it into
 
                        // a magnitude only.
                        if (r_divisor[(2*BW-2)])
                        if (r_divisor[(2*BW-2)])
                                r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)];
                                r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)];
 
                        //
 
                        // We only do this stage for a single clock, so go on
 
                        // with the rest of the divide otherwise.
                        pre_sign <= 1'b0;
                        pre_sign <= 1'b0;
                end else if (o_busy)
                end else if (r_busy)
                begin
                begin
                        r_bit <= r_bit + {(LGBW+1){1'b1}}; // r_bit = r_bit - 1;
                        // While the divide is taking place, we examine each bit
 
                        // in turn here.
 
                        //
 
                        r_bit <= r_bit + {(LGBW){1'b1}}; // r_bit = r_bit - 1;
                        r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
                        r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
                        if (|r_divisor[(2*BW-2):(BW)])
                        if (|r_divisor[(2*BW-2):(BW)])
                        begin
                        begin
                        end else if (diff[BW])
                        end else if (diff[BW])
                        begin
                        begin
 
                                // 
 
                                // diff = r_dividend - r_divisor[(BW-1):0];
 
                                //
 
                                // If this value was negative, there wasn't
 
                                // enough value in the dividend to support
 
                                // pulling off a bit.  We'll move down a bit
 
                                // therefore and try again.
 
                                //
                        end else begin
                        end else begin
 
                                //
 
                                // Put a '1' into our output accumulator.
 
                                // Subtract the divisor from the dividend,
 
                                // and then move on to the next bit
 
                                //
                                r_dividend <= diff[(BW-1):0];
                                r_dividend <= diff[(BW-1):0];
                                o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
                                o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
                                r_z <= 1'b0;
                                r_z <= 1'b0;
                        end
                        end
                end else if (r_sign)
                end else if (r_sign)
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                end
                end
 
 
        // Set Carry on an exact divide
        // Set Carry on an exact divide
        wire    w_n;
        wire    w_n;
        always @(posedge i_clk)
        always @(posedge i_clk)
                r_c <= (o_busy)&&((diff == 0)||(r_dividend == 0));
                r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0));
        assign w_n = o_quotient[(BW-1)];
        assign w_n = o_quotient[(BW-1)];
 
 
        assign o_flags = { 1'b0, w_n, r_c, r_z };
        assign o_flags = { 1'b0, w_n, r_c, r_z };
endmodule
endmodule
 
 
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