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[/] [zipcpu/] [trunk/] [rtl/] [core/] [div.v] - Diff between revs 160 and 174

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Rev 160 Rev 174
Line 55... Line 55...
        // assign       xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
        // assign       xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
 
 
        reg             r_sign, pre_sign, r_z, r_c, last_bit;
        reg             r_sign, pre_sign, r_z, r_c, last_bit;
        reg     [(LGBW-1):0]     r_bit;
        reg     [(LGBW-1):0]     r_bit;
 
 
 
        reg     zero_divisor;
 
        initial zero_divisor = 1'b0;
 
        always @(posedge i_clk)
 
                zero_divisor <= (r_divisor == 0)&&(r_busy);
 
 
        initial r_busy = 1'b0;
        initial r_busy = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_busy <= 1'b0;
                        r_busy <= 1'b0;
                else if (i_wr)
                else if (i_wr)
                        r_busy <= 1'b1;
                        r_busy <= 1'b1;
                else if ((last_bit)||(o_err))
                else if ((last_bit)||(zero_divisor))
                        r_busy <= 1'b0;
                        r_busy <= 1'b0;
 
 
        initial o_busy = 1'b0;
        initial o_busy = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        o_busy <= 1'b0;
                        o_busy <= 1'b0;
                else if (i_wr)
                else if (i_wr)
                        o_busy <= 1'b1;
                        o_busy <= 1'b1;
                else if (((last_bit)||(o_err))&&(~r_sign))
                else if (((last_bit)&&(~r_sign))||(zero_divisor))
                        o_busy <= 1'b0;
                        o_busy <= 1'b0;
                else if (~r_busy)
                else if (~r_busy)
                        o_busy <= 1'b0;
                        o_busy <= 1'b0;
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_rst)||(i_wr))
                if ((i_rst)||(i_wr))
                        o_valid <= 1'b0;
                        o_valid <= 1'b0;
                else if (r_busy)
                else if (r_busy)
                begin
                begin
                        if ((last_bit)||(o_err))
                        if ((last_bit)||(zero_divisor))
                                o_valid <= (o_err)||(~r_sign);
                                o_valid <= (zero_divisor)||(~r_sign);
                end else if (r_sign)
                end else if (r_sign)
                begin
                begin
                        // if (o_err), o_valid is already one.
                        o_valid <= (~zero_divisor); // 1'b1;
                        //      if not, o_valid has not yet become one.
 
                        o_valid <= (~o_err); // 1'b1;
 
                end else
                end else
                        o_valid <= 1'b0;
                        o_valid <= 1'b0;
 
 
 
        initial o_err = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if((i_rst)||(o_valid))
                if((i_rst)||(o_valid))
                        o_err <= 1'b0;
                        o_err <= 1'b0;
                else if (o_busy)
                else if (((r_busy)||(r_sign))&&(zero_divisor))
                        o_err <= (r_divisor == 0);
                        o_err <= 1'b1;
 
                else
 
                        o_err <= 1'b0;
 
 
        initial last_bit = 1'b0;
        initial last_bit = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if ((i_wr)||(pre_sign)||(i_rst))
                if ((i_wr)||(pre_sign)||(i_rst))
                        last_bit <= 1'b0;
                        last_bit <= 1'b0;
Line 170... Line 176...
                                //
                                //
                                r_dividend <= diff[(BW-1):0];
                                r_dividend <= diff[(BW-1):0];
                                o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
                                o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
                                r_z <= 1'b0;
                                r_z <= 1'b0;
                        end
                        end
 
                        r_sign <= (r_sign)&&(~zero_divisor);
                end else if (r_sign)
                end else if (r_sign)
                begin
                begin
                        r_sign <= 1'b0;
                        r_sign <= 1'b0;
                        o_quotient <= -o_quotient;
                        o_quotient <= -o_quotient;
                end
                end

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