| Line 96... |
Line 96... |
wire w_dcdB_pc, w_dcdB_cc;
|
wire w_dcdB_pc, w_dcdB_cc;
|
wire [3:0] w_cond;
|
wire [3:0] w_cond;
|
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
|
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
|
wire w_wR, w_rA, w_rB, w_wR_n;
|
wire w_wR, w_rA, w_rB, w_wR_n;
|
wire w_ljmp;
|
wire w_ljmp;
|
|
wire [31:0] iword;
|
generate
|
|
if (EARLY_BRANCHING != 0)
|
|
assign w_ljmp = (iword == 32'h7c87c000);
|
|
else
|
|
assign w_ljmp = 1'b0;
|
|
endgenerate
|
|
|
|
|
|
wire [31:0] iword;
|
|
`ifdef OPT_VLIW
|
`ifdef OPT_VLIW
|
reg [16:0] r_nxt_half;
|
reg [16:0] r_nxt_half;
|
assign iword = (o_phase)
|
assign iword = (o_phase)
|
// set second half as a NOOP ... but really
|
// set second half as a NOOP ... but really
|
// shouldn't matter
|
// shouldn't matter
|
| Line 117... |
Line 110... |
: i_instruction;
|
: i_instruction;
|
`else
|
`else
|
assign iword = { 1'b0, i_instruction[30:0] };
|
assign iword = { 1'b0, i_instruction[30:0] };
|
`endif
|
`endif
|
|
|
|
generate
|
|
if (EARLY_BRANCHING != 0)
|
|
assign w_ljmp = (iword == 32'h7c87c000);
|
|
else
|
|
assign w_ljmp = 1'b0;
|
|
endgenerate
|
|
|
|
|
assign w_op= iword[26:22];
|
assign w_op= iword[26:22];
|
assign w_mov = (w_op == 5'h0f);
|
assign w_mov = (w_op == 5'h0f);
|
assign w_ldi = (w_op[4:1] == 4'hb);
|
assign w_ldi = (w_op[4:1] == 4'hb);
|
assign w_cmptst = (w_op[4:1] == 4'h8);
|
assign w_cmptst = (w_op[4:1] == 4'h8);
|
assign w_ldixx = (w_op[4:1] == 4'h4);
|
assign w_ldixx = (w_op[4:1] == 4'h4);
|
