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[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Diff between revs 130 and 138

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Rev 130 Rev 138
Line 79... Line 79...
        output  wire            o_lock;
        output  wire            o_lock;
        output  reg             o_wR, o_rA, o_rB;
        output  reg             o_wR, o_rA, o_rB;
        output  wire            o_early_branch;
        output  wire            o_early_branch;
        output  wire    [(AW-1):0]       o_branch_pc;
        output  wire    [(AW-1):0]       o_branch_pc;
        output  wire            o_ljmp;
        output  wire            o_ljmp;
        output  reg             o_pipe;
        output  wire            o_pipe;
 
 
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
        wire                    o_dcd_early_branch;
        wire                    o_dcd_early_branch;
        wire    [(AW-1):0]       o_dcd_branch_pc;
        wire    [(AW-1):0]       o_dcd_branch_pc;
        reg     o_dcdI, o_dcdIz;
        reg     o_dcdI, o_dcdIz;
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
        reg     r_lock;
        reg     r_lock, r_pipe;
`endif
`endif
 
 
 
 
        wire    [4:0]    w_op;
        wire    [4:0]    w_op;
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev;
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
        wire            w_dcdR_pc, w_dcdR_cc;
        wire            w_dcdR_pc, w_dcdR_cc;
        wire            w_dcdA_pc, w_dcdA_cc;
        wire            w_dcdA_pc, w_dcdA_cc;
        wire            w_dcdB_pc, w_dcdB_cc;
        wire            w_dcdB_pc, w_dcdB_cc;
        wire    [3:0]    w_cond;
        wire    [3:0]    w_cond;
Line 131... Line 131...
        assign  w_cmptst = (w_op[4:1] == 4'h8);
        assign  w_cmptst = (w_op[4:1] == 4'h8);
        assign  w_ldilo  = (w_op[4:0] == 5'h9);
        assign  w_ldilo  = (w_op[4:0] == 5'h9);
        assign  w_ALU    = (~w_op[4]);
        assign  w_ALU    = (~w_op[4]);
 
 
        // 4 LUTs
        // 4 LUTs
 
        //
 
        // Two parts to the result register: the register set, given for
 
        // moves in i_word[18] but only for the supervisor, and the other
 
        // four bits encoded in the instruction.
 
        //
        assign  w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
        assign  w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
                                iword[30:27] };
                                iword[30:27] };
 
        // 2 LUTs
 
        //
 
        // If the result register is either CC or PC, and this would otherwise
 
        // be a floating point instruction with floating point opcode of 0,
 
        // then this is a NOOP.
 
        assign  w_noop   = (w_op[4:0] == 5'h18)&&(w_dcdR[3:1] == 3'h7);
 
 
        // 4 LUTs
        // 4 LUTs
        assign  w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
        assign  w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
                                iword[17:14] };
                                iword[17:14] };
 
 
        // 0 LUTs
        // 0 LUTs
Line 319... Line 331...
                        // already done the rest of the decode necessary to 
                        // already done the rest of the decode necessary to 
                        // settle between the other instructions.  For example,
                        // settle between the other instructions.  For example,
                        // o_FP plus these four bits uniquely defines the FP
                        // o_FP plus these four bits uniquely defines the FP
                        // instruction, o_DV plus the bottom of these defines
                        // instruction, o_DV plus the bottom of these defines
                        // the divide, etc.
                        // the divide, etc.
                        o_op <= (w_ldi)? 4'hf:w_op[3:0];
                        o_op <= (w_ldi)||(w_noop)? 4'hf:w_op[3:0];
 
 
                        // Default values
                        // Default values
                        o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
                        o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
                        o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
                        o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
Line 331... Line 343...
                        o_rA  <= w_rA;
                        o_rA  <= w_rA;
                        o_rB  <= w_rB;
                        o_rB  <= w_rB;
                        r_I    <= w_I;
                        r_I    <= w_I;
                        o_zI   <= w_Iz;
                        o_zI   <= w_Iz;
 
 
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst); // 1 LUT
                        // Turn a NOOP into an ALU operation--subtract in 
 
                        // particular, although it doesn't really matter as long
 
                        // as it doesn't take longer than one clock.  Note
 
                        // also that this depends upon not setting any registers
 
                        // or flags, which should already be true.
 
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT
                        o_M    <=  w_dcdM;
                        o_M    <=  w_dcdM;
                        o_DV   <=  w_dcdDV;
                        o_DV   <=  w_dcdDV;
                        o_FP   <=  w_dcdFP;
                        o_FP   <=  w_dcdFP;
 
 
                        o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
                        o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
Line 424... Line 441...
        //              by one
        //              by one
        // Note that we're not using iword here ... there's a lot of logic
        // Note that we're not using iword here ... there's a lot of logic
        // taking place, and it's only valid if the new word is not compressed.
        // taking place, and it's only valid if the new word is not compressed.
        //
        //
        reg     r_valid;
        reg     r_valid;
 
`ifdef  OPT_PIPELINED
 
        reg     r_pipe;
 
        initial r_pipe = 1'b0;
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_ce)
                if (i_ce)
                        o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
                        r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
                                &&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
                                &&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
                                &&(i_instruction[17:14] == o_dcdB[3:0])
                                &&(i_instruction[17:14] == o_dcdB[3:0])
                                &&(i_instruction[17:14] != o_dcdA[3:0])
                                &&(i_instruction[17:14] != o_dcdA[3:0])
                                &&(i_gie == o_gie)
                                &&(i_gie == o_gie)
                                &&((i_instruction[21:19]==o_cond[2:0])
                                &&((i_instruction[21:19]==o_cond[2:0])
                                        ||(o_cond[2:0] == 3'h0))
                                        ||(o_cond[2:0] == 3'h0))
                                &&((i_instruction[13:0]==r_I[13:0])
                                &&((i_instruction[13:0]==r_I[13:0])
                                        ||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
                                        ||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
 
        assign o_pipe = r_pipe;
 
`else
 
        assign o_pipe = 1'b0;
 
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_valid <= 1'b0;
                        r_valid <= 1'b0;
                else if ((i_ce)&&(o_ljmp))
                else if ((i_ce)&&(o_ljmp))
                        r_valid <= 1'b0;
                        r_valid <= 1'b0;

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