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[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Diff between revs 201 and 205

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Rev 201 Rev 205
Line 53... Line 53...
//
//
//
//
module  idecode(i_clk, i_rst, i_ce, i_stalled,
module  idecode(i_clk, i_rst, i_ce, i_stalled,
                i_instruction, i_gie, i_pc, i_pf_valid,
                i_instruction, i_gie, i_pc, i_pf_valid,
                        i_illegal,
                        i_illegal,
 
                o_valid,
                o_phase, o_illegal,
                o_phase, o_illegal,
                o_pc, o_gie,
                o_pc, o_gie,
                o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
                o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
                o_cond, o_wF,
                o_cond, o_wF,
                o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
                o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
Line 70... Line 71...
        input                   i_clk, i_rst, i_ce, i_stalled;
        input                   i_clk, i_rst, i_ce, i_stalled;
        input   [31:0]           i_instruction;
        input   [31:0]           i_instruction;
        input                   i_gie;
        input                   i_gie;
        input   [(AW-1):0]       i_pc;
        input   [(AW-1):0]       i_pc;
        input                   i_pf_valid, i_illegal;
        input                   i_pf_valid, i_illegal;
        output  wire            o_phase;
        output  wire            o_valid, o_phase;
        output  reg             o_illegal;
        output  reg             o_illegal;
        output  reg     [AW:0]   o_pc;
        output  reg     [AW:0]   o_pc;
        output  reg             o_gie;
        output  reg             o_gie;
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
        output  wire    [31:0]   o_I;
        output  wire    [31:0]   o_I;
Line 103... Line 104...
        reg     r_pipe;
        reg     r_pipe;
`endif
`endif
 
 
 
 
        wire    [4:0]    w_op;
        wire    [4:0]    w_op;
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev,
 
                        w_noop, w_lock;
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
        wire            w_dcdR_pc, w_dcdR_cc;
        wire            w_dcdR_pc, w_dcdR_cc;
        wire            w_dcdA_pc, w_dcdA_cc;
        wire            w_dcdA_pc, w_dcdA_cc;
        wire            w_dcdB_pc, w_dcdB_cc;
        wire            w_dcdB_pc, w_dcdB_cc;
        wire    [3:0]    w_cond;
        wire    [3:0]    w_cond;
        wire            w_wF, w_mem, w_sto, w_lod, w_div, w_fpu;
        wire            w_wF, w_mem, w_sto, w_div, w_fpu;
        wire            w_wR, w_rA, w_rB, w_wR_n;
        wire            w_wR, w_rA, w_rB, w_wR_n;
        wire            w_ljmp, w_ljmp_dly, w_cis_ljmp;
        wire            w_ljmp, w_ljmp_dly, w_cis_ljmp;
        wire    [31:0]   iword;
        wire    [31:0]   iword;
 
 
 
 
Line 215... Line 217...
        // 2 LUTs
        // 2 LUTs
        //
        //
        // If the result register is either CC or PC, and this would otherwise
        // If the result register is either CC or PC, and this would otherwise
        // be a floating point instruction with floating point opcode of 0,
        // be a floating point instruction with floating point opcode of 0,
        // then this is a NOOP.
        // then this is a NOOP.
 
        assign  w_lock   = (!iword[31])&&(w_op[4:0]==5'h1d)&&(
 
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
 
                                ||(IMPLEMENT_FPU==0));
        assign  w_noop   = (!iword[31])&&(w_op[4:0] == 5'h1f)&&(
        assign  w_noop   = (!iword[31])&&(w_op[4:0] == 5'h1f)&&(
                        ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
                        ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
                        ||(IMPLEMENT_FPU==0));
                        ||(IMPLEMENT_FPU==0));
 
 
        // dcdB - What register is used in the opB?
        // dcdB - What register is used in the opB?
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                        { (iword[21:19]==3'h0), iword[21:19] };
                        { (iword[21:19]==3'h0), iword[21:19] };
 
 
        // 1 LUT
        // 1 LUT
        assign  w_mem    = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00);
        assign  w_mem    = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00);
        assign  w_sto     = (w_mem)&&( w_cis_op[0]);
        assign  w_sto     = (w_mem)&&( w_cis_op[0]);
        assign  w_lod     = (w_mem)&&(!w_cis_op[0]);
 
        // 1 LUT
        // 1 LUT
        assign  w_div     = (!iword[31])&&(w_op[4:1] == 4'h7);
        assign  w_div     = (!iword[31])&&(w_op[4:1] == 4'h7);
        // 2 LUTs
        // 2 LUTs
        assign  w_fpu   = (!iword[31])&&(w_op[4:3] == 2'b11)
        assign  w_fpu   = (!iword[31])&&(w_op[4:3] == 2'b11)
                                &&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00);
                                &&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00);
Line 401... Line 405...
                begin
                begin
`ifdef  OPT_CIS
`ifdef  OPT_CIS
                        if (!o_phase)
                        if (!o_phase)
                                o_gie<= i_gie;
                                o_gie<= i_gie;
 
 
                        if ((iword[31])&&(!o_phase))
                        if (iword[31])
 
                        begin
 
                                if (o_phase)
 
                                        o_pc <= o_pc + 1'b1;
 
                                else if (i_pf_valid)
                                o_pc <= { i_pc, 1'b1 };
                                o_pc <= { i_pc, 1'b1 };
                        else if ((iword[31])&&(i_pf_valid))
                        end else begin
                                o_pc <= { i_pc, 1'b0 };
                                // The normal, non-CIS case
                        else
 
                                o_pc <= { i_pc + 1'b1, 1'b0 };
                                o_pc <= { i_pc + 1'b1, 1'b0 };
 
                        end
`else
`else
                        o_gie<= i_gie;
                        o_gie<= i_gie;
                        o_pc <= { i_pc + 1'b1, 1'b0 };
                        o_pc <= { i_pc + 1'b1, 1'b0 };
`endif
`endif
 
 
Line 458... Line 466...
 
 
                        o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&(
                        o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&(
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
                                ||(IMPLEMENT_FPU==0));
                                ||(IMPLEMENT_FPU==0));
`ifdef  OPT_PIPELINED
`ifdef  OPT_PIPELINED
                        r_lock  <= (!iword[31])&&(w_op[4:0]==5'h1d)&&(
                        r_lock  <= w_lock;
                                ((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
 
                                ||(IMPLEMENT_FPU==0));
 
`endif
`endif
`ifdef  OPT_CIS
`ifdef  OPT_CIS
                        r_nxt_half <= { iword[31], iword[14:0] };
                        r_nxt_half <= { iword[31], iword[14:0] };
`endif
`endif
 
 
Line 586... Line 592...
`endif
`endif
 
 
        always @(posedge i_clk)
        always @(posedge i_clk)
                if (i_rst)
                if (i_rst)
                        r_valid <= 1'b0;
                        r_valid <= 1'b0;
                else if ((i_ce)&&(o_ljmp))
                else if (i_ce)
                        r_valid <= 1'b0;
                        r_valid <= ((i_pf_valid)||(o_phase)||(i_illegal))
                else if ((i_ce)&&(i_pf_valid))
                                        &&(!o_ljmp)&&(!o_early_branch);
                        r_valid <= 1'b1;
                else if (!i_stalled)
                else if (~i_stalled)
 
                        r_valid <= 1'b0;
                        r_valid <= 1'b0;
 
 
 
        assign  o_valid = r_valid;
 
 
 
 
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
 
 
endmodule
endmodule
 
 
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